DS643 Datasheet, PDF (132/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
SDMA Error Conditions
The SDMA performs several error checking functions to ensure proper operation of the DMA engine. If an error
occurs then the channel on which the error is detected is halted, and the channel status register Error bit for the
channel is set to 1. If possible, the Error bit for the current descriptor is set to 1 also; although, depending on the
error condition, this might not get updated to remote memory.
To recover from an error condition the SDMA must be reset either by a hard reset or by issuing a soft reset (such as
setting SwReset = 1 in the DMA Control register. Table 70 lists the possible errors that can be flagged and their
causes.
Table 70: Descriptor Errors
Error
TX_CHNL_STS.CurPErr
RX_CHNL_STS.CurPErr
TX_CHNL_STS.TailPErr
RX_CHNL_STS.TailPErr
TX_CHNL_STS.NxtPErr
RX_CHNL_STS.NxtPErr
TX_CHNL_STS.AddrErr
RX_CHNL_STS.AddrErr
TX_CHNL_STS.CmpErr
RX_CHNL_STS.CmpErr
TX_CHNL_STS.BsyWr
RX_CHNL_STS.BsyWr
Description
Current Descriptor Pointer Error
This error occurs if the Current Descriptor Pointer does not fall within the <prefix>_BASEADDR to
<prefix>_HIGHADDR range⁽¹⁾. Descriptors must reside within memory as mapped by the base address and
high address of the NPI. Addresses outside this range are detected and flagged as errors.
Tail Descriptor Pointer Error
This error occurs if the Tail Descriptor Pointer does not fall within the <prefix>_BASEADDR to
<prefix>_HIGHADDR range. Descriptors must reside within memory as mapped by the base address and
high address of the NPI. Addresses outside this range are detected and flagged as errors.
Next Descriptor Pointer Error
This error occurs if the Next Descriptor Pointer does not fall within the <prefix>_BASEADDR to
<prefix>_HIGHADDR range⁽¹⁾. Descriptors must reside within memory as mapped by the base address and
high address of the NPI Addresses outside this range are detected and flagged as errors.
Buffer Address Error
This error occurs if the Buffer Address does not fall within the <prefix>_BASEADDR to <prefix>_HIGHADDR
range⁽¹⁾.
All transmit and receive data buffers must reside within memory as mapped by the base address and high
address of the NPI.
Addresses outside this range are detected and flagged as errors.
Complete Bit Error
This error occurs if a descriptor is fetched with the Complete bit set to 1 (as in STS_CTRL_APP0.Completed
=1).
This error indicates that a descriptor, which had been already used by SDMA, is being processed again, before
the software application has had a chance to process the descriptor and associated data buffer.
This error checking can be disabled or enabled by setting/clearing C_COMPLETED_ERR_TX and
C_COMPLETED_ERR_RX for the associated channel.
Setting the parameters to 1 enables checking and setting the parameters to 0 disables checking.
Busy Write Error
This error occurs if the Current Descriptor Pointer register is written to through the PLBv4.6 slave port while the
SDMA engine is busy.
Examining TX_CHNL_STS.EngBusy and RX_CHNL_STS.EngBusy for the respective channel indicates to the
software application whether or not the channel is busy.
If EngBsy = 1 then the channel is busy and the Current Descriptor Pointer should not be written to by the
software application.
Notes:
1. where: C_ALL_PIMS_SHARE_ADDRESSES =
0:<prefix> = C_MPMC
1:<prefix> = C_PIM<Port_Num>
DS643 February 22, 2013
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Product Specification