DS643 Datasheet, PDF (24/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
NPI PIM I/O Signals
The NPI PIM runs only at a 1:1 clock ratio to the MPMC memory clock (PORT MPMC_Clk0); consequently, there is
no clock input for this interface. Table 20 lists the NPI PIM I/O signals.
Table 20: NPI PIM I/O Signals
Signal Name
Direction
Address Phase Related Input Ports
PIM<Port_Num>_Addr
Input
PIM<Port_Num>_AddrReq
Input
PIM<Port_Num>_RNW
Input
PIM<Port_Num>_Size
Input
PIM<Port_Num>_RdModWr
Input
Other Outputs
PIM<Port_Num>_InitDone
Output
Address Phase Related Output Ports
PIM<Port_Num>_AddrAck
Output
Write Data Phase Related Input Ports
PIM<Port_Num>_WrFIFO_Data
Input
PIM<Port_Num>_WrFIFO_BE
Input
Init Status
Description
Indicates the starting address of a particular request.
x
Only valid when PIM<Port_Num>_AddrReq is valid. Must be
aligned to PIM<Port_Num>_Size burst length.
See Address Path, page 55 for address alignment requirements.
This active-High signal indicates that NPI is ready for MPMC to
arbitrate an address request. This request cannot be aborted.
x
Must be asserted until PIM<Port_Num>_AddrAck is asserted.
See NPI Design Restrictions and Recommendations, page 171
for additional restrictions.
Read/Not Write:
x
0 = Request is a Write request.
1 = Request is a Read request.
Only valid when PIM<Port_Num>_AddrReq is valid.
Indicates the transfer type of the request:
• 0x0 = Word transfers (32-bit NPI only)
• 0x0 = Doubleword transfers (64-bit NPI only)
• 0x1 = 4-word cache-line transfer
• 0x2 = 8-word cache-line transfers
x
• 0x3 =16-word burst transfers
• 0x4 = 32-word burst transfers
• 0x5 = 64-word burst transfers (Not available in all
configurations. Available configurations are described in
Restrictions on 64-Word Burst Transfers, page 173.)
• Only valid when PIM<Port_Num>_AddrReq is valid.
This active-High signal indicates that if the request is a write,
MPMC should do a read/ modify/write.
Only valid when PIM<Port_Num>_AddrReq is valid.
Only valid when C_INCLUDE_ECC_SUPPORT is set to 1.
This is required to be set to 1, if:
x
• The total transfer size specified by PIM<Port_Num>_Size *
32 (bits/word) is less than C_MEM_DATA_WIDTH * 4
(beats/burst), to satisfy the constant memory burst length of 4.
• The PIM<Port_Num>_WrFIFO_BE bits for the transfer are
not guaranteed to be 1, because MPMC ECC does not use
data mask (DM) signals.
1 indicates that initialization is complete and that FIFOs are
available for use. Do not assert
0
PIM<Port_Num>_WrFIFO_Push or
PIM<Port_Num>_RdFIFO_Pop until
PIM<Port_Num>_InitDone is equal to 1.
This active-High signal indicates that MPMC has begun
arbitration for address request. Valid for one cycle of
0
MPMC_Clk0.
PIM<Port_Num>_AddrReq must be deasserted on the next
cycle of MPMC_Clk0 unless NPI is requesting a new transfer.
Data to be pushed into MPMC write FIFOs.
x
Only valid with PIM<Port_Num>_WrFIFO_Push.
Data is little-endian as shown in Figure 7, page 84.
x
Indicates which bytes of PIM<Port_Num>_WrFIFO_Data to
write. Only valid with PIM<Port_Num>_WrFIFO_Push.
DS643 February 22, 2013
www.xilinx.com
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Product Specification