DS643 Datasheet, PDF (215/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
Reference Documents
• Product Pages and Solution Centers:
• Embedded Development Kit (EDK) page: www.xilinx.com/support/documentation/dt_edk.htm
• ISE tool documentation page: www.xilinx.com/support/documentation/dt_ise.htm
• MIG Solution Center: www.xilinx.com/support/answers/34263.htm
• Spartan-3 generation FPGAs page: www.xilinx.com/products/spartan3a/3a.htm
• Virtex-4 FPGA page: www.xilinx.com/support/documentation/virtex-4.htm
• Virtex-5 FPGA pages:
- www.xilinx.com/support/documentation/virtex-5.htm (Documentation)
- www.xilinx.com/products/virtex5 (Product)
• Virtex-6 FPGA page: www.xilinx.com/products/silicon-devices/fpga/virtex-6
• Spartan-6 FPGA page: www.xilinx.com/support/documentation/spartan-6.htm
• Development boards page: www.xilinx.com/products/boards-and-kits
• LocalLink User Interface page: www.xilinx.com/aurora/aurora_member/sp006.pdf
• Video Starter Kit page: www.xilinx.com/products/devboards/reference_design/vsk_s3/vsk_s3.htm
• To locate these Xilinx documents, go to www.xilinx.com/support:
• MicroBlaze Processor User Guide (UG081)
• Spartan-6 FPGA Memory Controller User Guide (UG388)
• Virtex-6 FPGA Memory Interface Solutions User Guide (UG406)
• Spartan-6 FPGA Memory Interface Solutions User Guide (UG416)
• Constraints Guide (UG625)
• XAPP768c, Interfacing Spartan-3 Devices With 166 MHz or 333 Mb/s DDR SDRAM Memories:
www.xilinx.com/support/software/memory/protected/XAPP768c.pdf
• DDR2 SDRAM Interface for Spartan-3 Generation FPGAs (XAPP454)
• DDR2 SDRAM Physical Layer Using Direct-Clocking Technique (XAPP701)
• DDR SDRAM Controller Using Virtex-5 FPGA Devices (XAPP851)
• High-Performance DDR2 SDRAM Interface in Virtex-5 Devices (XAPP858)
• Documents in the EDK Install Directory:
• Embedded Processor Block in Virtex-5 FPGAs Reference Guide
<EDK Install Directory>/doc/usenglish/embedproc_ug200.pdf
• Specification for PLB v4.6 Bus Protocol with Xilinx Simplifications, SP026,
<EDK Install Directory>/doc/usenglish/sp026.pdf
• PLB v3.6 and OPB to PLB v4.6 System and Core Migration User Guide:
<EDK Install Directory>/doc/usenglish/mg_ug.pdf
• IBM CoreConnect documentation: www.xilinx.com/products/ipcenter/dr_pcentral_coreconnect.htm
• CoreConnect Device Control Register Bus: Architecture Specification
• IBM CoreConnect 64-Bit Processor Local Bus: Architecture Specification
• IBM CoreConnect 64-Bit On-Chip Peripheral Bus: Architectural Specification
• Answer Records (useful design, debug, and implementation): www.xilinx.com/xlnx/xil_ans_browser.jsp
• www.xilinx.com/support/answers/38476.htm
• www.xilinx.com/support/answers/24912.htm
DS643 February 22, 2013
www.xilinx.com
215
Product Specification