DS643 Datasheet, PDF (117/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
Alternatively, a Clock Generator IP core can be used to drive the MCB clocks. Instead of using pll_module, it can be
replaced by the clock_generator core as shown in the following code example:
BEGIN clock_generator
PARAMETER INSTANCE = clock_generator_0
PARAMETER HW_VER = 4.00.a
PARAMETER C_CLKIN_FREQ = 200000000
PARAMETER C_CLKOUT0_FREQ = 800000000
PARAMETER C_CLKOUT0_PHASE = 180
PARAMETER C_CLKOUT0_GROUP = PLL0
PARAMETER C_CLKOUT0_BUF = FALSE
PARAMETER C_CLKOUT1_FREQ = 800000000
PARAMETER C_CLKOUT1_PHASE = 0
PARAMETER C_CLKOUT1_GROUP = PLL0
PARAMETER C_CLKOUT1_BUF = FALSE
PARAMETER C_CLKOUT2_FREQ = 100000000
PARAMETER C_CLKOUT2_PHASE = 0
PARAMETER C_CLKOUT2_GROUP = PLL0
PARAMETER C_CLKOUT2_BUF = TRUE
PORT CLKIN = dcm_clk_s
PORT CLKOUT0 = pll_module_0_CLKOUT0
PORT CLKOUT1 = pll_module_0_CLKOUT1
PORT CLKOUT2 = pll_module_0_CLKOUT2
PORT RST = sys_rst
PORT LOCKED = pll_module_0_LOCKED
END
PIM Clocking
All PIM types except the MCB PIM type have a base clock that is taken from the port MPMC_Clk0. MPMC_Clk0 must
be shared across all PIMs except MCB PIMs. MCB PIMs are the only PIMs that can be asynchronously clocked from
other PIMs.
The MPMC_Clk0 clock that the PIMs run on can be separate and asynchronous from the MPMC_Clk_Mem_2x memory
clock. Additionally, some PIM types support an optional 1:1 or 1:2 clock ratio from their base PIM clock. It is
recommended that MPMC_Clk0 is generated so the PIMs run at a 1:1 clock ratio.
For example, it is possible to have an MPMC clocked as follows:
• MPMC_Clk_Mem_2x = 800 MHz
• MPMC_MCB_DRP_Clk = 100 MHz
• MPMC_Clk0 = 90 MHz (asynchronous to MPMC_Clk_Mem_2x)
• Port 0 PLB PIM can connect to a PLB bus that must be 45 or 90 MHz (synchronous to MPMC_Clk0)
• Port 1 XCL PIM can connect to an XCL interface that must be 45 or 90 MHz (synchronous to MPMC_Clk0)
• Port 2 MCB PIM can run at 87 MHz (asynchronous to all other clocks)
• Port 3 NPI PIM must run at 90 MHz using the same clock as MPMC_Clk0
Special Clocking Requirements: When Two MCBs Are On The Same Side of The Device
In a system where two instances of MPMC are on the same side of the device (both on the left or both on the right),
it is necessary for both of them to share a single BUFPLL_MCB instance instead of one for each MPMC instance. This
situation is only possible on devices with four MCB sites.
When two instances of MPMC are on the same side of the device, the second MPMC must be set with
parameter C_MCB_USE_EXTERNAL_BUFPLL == 1. In this case, the first MPMC instantiates the BUFPLL_MCB.
DS643 February 22, 2013
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117
Product Specification