DS643 Datasheet, PDF (118/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
These signals would then be connected to the second MPMC in the MHS file and the outputs of the internal
BUFPLL_MCB in the first MPMC drive the MPMC_Clk_Mem_2x_bufpll_o, MPMC_Clk_Mem_2x_180_bufpll_o,
MPMC_Clk_Mem_2x_CE0_bufpll_o, MPMC_Clk_Mem_2x_CE90_bufpll_o, and MPMC_PLL_Lock_bufpll_0 ports
and would then drive the MPMC_Clk_Mem_2x, MPMC_Clk_Mem_2x_180, MPMC_Clk_Mem_2x_CE0,
MPMC_Clk_Mem_2x_CE90 and MPMC_PLL_Lock ports of the second MPMC.
When two MPMCs are located on the same side of the device, they must both operate on the same memory clock.
The following is a Microprocessor Hardware Specification (MHS) file example of how the two MPMCs use
cascaded clock connections when they are both located on the same side of the device:
BEGIN mpmc
PARAMETER INSTANCE = MPMC_0
...
PORT MPMC_Clk_Mem_2x_bufpll_o = MPMC_Clk_Mem_2x_bufpll_o
PORT MPMC_Clk_Mem_2x_180_bufpll_o = MPMC_Clk_Mem_2x_180_bufpll_o
PORT MPMC_Clk_Mem_2x_CE0_bufpll_o = MPMC_Clk_Mem_2x_CE0_bufpll_o
PORT MPMC_Clk_Mem_2x_CE90_bufpll_o = MPMC_Clk_Mem_2x_CE90_bufpll_o
PORT MPMC_PLL_Lock_bufpll_o = MPMC_PLL_Lock_bufpll_o
END
BEGIN mpmc
PARAMETER INSTANCE = MPMC_1
PARAMETER C_MCB_USE_EXTERNAL_BUFPLL = 1
...
PORT MPMC_Clk_Mem_2x = MPMC_Clk_Mem_2x_bufpll_o
PORT MPMC_Clk_Mem_2x_180 = MPMC_Clk_Mem_2x_180_bufpll_o
PORT MPMC_Clk_Mem_2x_CE0 = MPMC_Clk_Mem_2x_CE0_bufpll_o
PORT MPMC_Clk_Mem_2x_CE90 = MPMC_Clk_Mem_2x_CE90_bufpll_o
PORT MPMC_PLL_Lock = MPMC_PLL_Lock_bufpll_o
END
Special Restrictions on Connection/Routing of MPMC_PLL_Lock Input
The MPMC_PLL_Lock input of the MPMC must be connected directly to the LOCKED output signal of the PLL driving
the MPMC_Clk_Mem_2x and MPMC_Clk_Mem_2x inputs (except for the second cascaded MPMC on the same side of
the device). There can be no logic between the LOCKED output of the PLL and the primary MPMC_PLL_Lock input of
the MPMC, otherwise the Place and Route tool (PAR) issues an error about an unroutable signal into the
BUFPLL_MCB element inside MPMC.
If logic needs to be generated from the attached LOCKED output of the PLL, the MPMC_PLL_Lock_bufpll_o output
of MPMC should be used because it reflects the state of the PLL lock including the BUFPLL_MCB element driving the
memory clock. The BUFPLL_MCB element requires a special direct connection route to the LOCKED output of the PLL
for it to function properly in driving the memory clock to the MCB.
In some cases when multiple PLLs are needed in a system, you might need to instantiate separate instances of
clock_generator to ensure that its LOCKED output signal is driven from only a single PLL output to the MPMC.
DS643 February 22, 2013
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Product Specification