DS643 Datasheet, PDF (178/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
8-Word, Cacheline Read
Figure 47 shows the following:
• A 64-bit NPI.
• An 8-word cacheline read transfer.
• The address is acknowledged in the same cycle as it is requested.
• The address is on a doubleword boundary.
• The RdFIFO_RdWdAddr indicates that data is returned target-word first.
• There are three cases of possible RdFIFO_Latency values.
X-Ref Target - Figure 47
MPMC_CLK0
AddrReq
AddrAck
Addr[31:0]
0x8
RNW
Size[3:0]
0x2
RdModWr
InitDone
RdFIFO_Empty
RdFIFO_Pop
RdFIFO_Flush
RdFIFO_Latency[1:0]
RdFIFO_Data[63:0]
RdFIFO_RdWdAddr[3:0]
RdFIFO_Latency[1:0]
RdFIFO_Data[63:0]
RdFIFO_RdWdAddr[3:0]
RdFIFO_Latency[1:0]
RdFIFO_Data[63:0]
RdFIFO_RdWdAddr[3:0]
0x0
D0
D1
D2
D3
0x2
0x4
0x6
0x0
0x1
D0
D1
0x2
0x4
D2
D3
0x6
0x0
0x2
D0
0x2
D1
D2
D3
0x4
0x6
0x0
Figure 47: 64-Bit NPI 8-Word Cacheline Read
Case 1
Case 2
Case 3
X11045
DS643 February 22, 2013
www.xilinx.com
178
Product Specification