DS643 Datasheet, PDF (203/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
VFBC PIM Latency and Throughput
The VFBC PIM uses the NPI interface of the MPMC, therefore the latency and throughput of the VFBC PIM is
similar to the NPI PIM. The maximum throughput of the VFBC PIM is 95.2% of the NPI PIM throughput (see
Table 95, page 194). The VFBC uses 32-word bursts and 64-bit NPI interface only; consequently, only those
configurations from Table 95, page 194 are valid for the VFBC numbers.
The VFBC PIM adds an additional 68 MPMC_Clk cycles for the first 32-word burst of each VFBC command. Each
subsequent burst does not have an additional latency cost. The minimum number of cycles between each 32-word
burst transaction is 0 MPMC_Clk cycles. This number increases if the VFBC or MPMC FIFOs are not ready.
For Write transactions, data is written into the NPI interface starting at 8 MPMC_Clk cycles before the NPI address
request is asserted. (A complete Write transaction takes 16 MPMC_Clk cycles only for 32-word bursts.)
Resource Utilization
The following subsections detail the MPMC resource utilization:
• Resource (Block RAM) Utilization
• Resource (LUT, Flip-Flop, and Slice) Utilization
Resource (Block RAM) Utilization
By default, the MPMC uses block RAM based FIFOs in each of its ports to buffer read and write data from the
external memory to improve memory efficiency, reduce LUT utilization, and to improve timing. The MPMC also
provides a per-port parameter called C_PI<Port_Num>_RD_FIFO_TYPE and C_PI<Port_Num>_WR_FIFO_TYPE
which can be used to disable FIFOs for (read-only or write-only ports) or to choose the use of SRL FIFOs instead of
block RAM FIFOs.
MPMC block RAM utilization is outlined as follows:
• 1 block RAM for control state machine.
• 1 block RAM for arbitration if CUSTOM arbitration algorithm is used (C_ARB0_ALGO = CUSTOM). For FIXED
or ROUND_ROBIN arbitration, no block RAM is used. If only 1 port is used, no block RAM is used.
• If ECC is enabled, 1 block RAM is used for 8-, 16-, and 32-bit DDR/DDR2 memories, and two block RAMs for
64-bit DDR/DDR2 memories.
• 1 block RAM for every port where a Performance Monitor is enabled.
Table 99 shows the block RAM usage for each Read and Write port for the Spartan-3, Virtex-4, and Virtex-5 devices.
Table 99: Read and Write Port Block RAM Usage (Spartan-3, Virtex-4, and Virtex-5 FPGAs)
0 block RAMs if write-only port (C_PI<Port_Num>_RD_FIFO_TYPE = DISABLED).
1 block RAM for 32-bit NPI⁽¹⁾ port width and 8/16-bit DDR/DDR2 memory.
1 block RAM for 32-bit NPI port width and 8/16/32-bit SDRAM.
Read Ports _{2 block RAMs for 64-bit NPI port width or 32-bit DDR/DDR2 memory or 64-bit SDRAM.}
On Virtex-5 FPGAs, there is an optimization where 1 block RAM is used for 64-bit NPI with 32-bit DDR and DDR2 or 64-bit
SDRAM.
4 block RAMs for 64-bit DDR and DDR2 memory.
1. NPI Width is defined as: SDMA = 64 bits, XCL = 32 bits PLB PIM = value of parameter C_SPLB<Port_Num>_NATIVE_DWIDTH (the default is 64 and
this value must be 64 for IPLB and DPLB SUBTYPES), NPI = value of parameter C_PIM<Port_Num>_DATA_WIDTH (default is 64).
DS643 February 22, 2013
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Product Specification