DS643 Datasheet, PDF (213/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
Data Path Configuration
In the Data Path Configuration tab (which is not valid for Spartan-6), you can configure the common datapath
(pipeline) settings and the individual settings for each port.
• General Pipeline Settings let you set the Write TML Pipeline checkbox and set the Read Pipeline Fanout
value.
• Port-specific Settings let you change the pipeline settings for the individual ports as follows:
- Read FIFO Config: Implement FIFO using block RAM, SRL, or Wr-Only (Write Only, Read FIFO
Disabled).
- Write FIFO Config: Implement FIFO using block RAM, SRL, or Rd-Only (Read Only, Write FIFO
Disabled).
- Read Memory Pipeline: Enable pipeline for read access to memory.
- Read Port Pipeline: Enable pipeline for read access to the underlying port.
- Write Memory Pipeline: Enable pipeline for write access to memory.
- Write Port Pipeline: Enable pipeline for write access to port.
- Address Ack Pipeline: Enable pipeline for acknowledgement of address request.
Arbitration
MPMC has a maximum of eight ports that can all access the memory at the same time. Consequently, it is very
important to have an arbitration algorithm to determine which port has priority at any given moment. In the
Arbitration tab, you can choose what arbitration algorithm to use.
• Arbitration Settings: From the Select Arbitration Algorithm box, select one of the three following arbitration
algorithms:
- Round Robin: Perform Round Robin arbitration.
- Fixed: Perform Fixed priority arbitration. When set to Fixed, the priority order is from lowest number port
to highest number port and cannot be changed (Time Slot 0 is greyed out and is not available for edit.)
- Custom: In this mode, you can customize the number of time slots, as well as the arbitration priorities in
each time slot. The arbitration priority in each time slot is encoded as a string to indicate decreasing
priorities among ports.
For example, the string “01234567” gives the highest priority to port 0, then decreasing priorities from
port 1 through port 7.
• Turn on Arbiter Pipeline checkbox
• Number of Time Slots: Set the number of time slots
• Restore Arbitration Defaults
• Time Slots: 1 through 15
ECC/PM/PHY/DBG
All debug registers, ECC registers and Performance Monitors are accessed using a Control Bus interface. With
Virtex-6 and Spartan-6 devices some of these options might not be available.
In the General ECC/PM/PHY/DBG Settings box, you can enable Debug, ECC, and PM. If any one of them is
enabled, the Control Bus is activated and you must enter the base address in the Control Base Address box. After
you enable ECC, you can configure the behavior further in the ECC Settings box. After you enable PM, you can
change the general parameters of the Performance Monitor in the Common Performance Monitor Settings box, and
the port-specific parameters in Port-specific Performance Monitor Settings box.
DS643 February 22, 2013
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Product Specification