DS643 Datasheet, PDF (58/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
The number of block RAM or SRL resources consumed by the FIFOs depends on the:
• Number of ports and whether a particular port has read FIFOs, write FIFOs, or both
• NPI data width and memory data width
See the Resource Utilization, page 203 for more information about block RAM utilization in the MPMC. This section
also explains how many LUTs are used when a SRL FIFO is selected.
Read Word Address
When Read data for a cacheline request is returned, it might not be returned target-word first. Read data is returned
sequentially, but it could be returned where the requested target word appears later in the sequence than desired
due to memory access optimizations and the allowance of back-to-back read requests.
You must monitor the PIM<Port_Num>_RdFIFO_RdWdAddr output value to determine which word is being
returned first.
Data Path Pipelines
Table 39 outlines the pipeline stages in the MPMC datapath; which is set using the MPMC interface. See the IP
Configuration Graphical User Interface, page 209 for more information about setting the pipeline. Adding pipeline
stages improves timing but also increases latency.
Table 39: MPMC Data Path Pipelines
Pipeline Stage
Description
Write Data Path input
Registers the write FIFO inputs (push, FIFO address, data, byte enables).
Write Data Path output
Registers the write FIFO outputs (data, byte enables). All ports must have the same setting.
Write Data Path timing
management
There is a multiplexer (MUX) that selects which write FIFO the PHY is currently using. This
pipeline stage adds a register after that MUX.
Read Data Path input
Registers the read FIFO inputs (push, FIFO address, data). All ports must have the same
setting.
Read Data Path output
Registers the read FIFO outputs (data, read word address).
Read Data Path fanout
The read data going from the PHY to the datapath is routed to the read FIFO for each port.
If the FIFOs are spaced far apart (which is likely when using block RAM FIFOs), the routing
delays can be large
Setting the fanout has the following effect:
0 = No register is instantiated.
1 = Read data is forwarded from the PHY for up to eight sets of registers. The outputs of the
registers are then forwarded on to a maximum of one read FIFO.
2 = Read data is forwarded from the PHY to up to four sets of registers. The outputs of the
registers are the forwarded on to a maximum of two read FIFOs.⁽¹⁾
4 = Read data is forwarded from the PHY to two sets of registers. The outputs of the registers
are the forwarded on to a maximum of four read FIFOs.⁽¹⁾
8 = Read data is forwarded from the PHY to a single register, then forwarded on to each of
the read FIFOs.
Notes:
1. Values of 3, 5, 6, 7 are invalid.
Control Path / Arbiter
The MPMC control path is configured for optimal memory bandwidth given a particular memory. It can be
configured to support different physical (PHY) interfaces also.
DS643 February 22, 2013
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Product Specification