DS643 Datasheet, PDF (69/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
ECC Status Register
The ECC Status register (ECCS) in combination with the ECC Error Address register (ECCADDR) records the first
occurrence of an error and latches information about the error until the error is cleared by writing to the ECCS.
Table 44 describes the bit values for the ECC Status register.
Table 44: ECCS Status Register Bit Definitions
Bit(s)
Name
Core
Access
Reset
Value
Description
0:15
Reserved
16:19
ECC_ERR_SIZE R/ROW⁽¹⁾
0000
ECC Error Transaction Size. Records the size of the NPI
transaction where the error occurred. For ECC_ERR_SIZE
field values, see Table 20, page 24 under the signal name
PIM<Port_Num>_Size.
ECC ERROR Transaction Read/Write: Indicates if error
occurred on a read transactions or a write transaction that
20
ECC_ERR_RNW R/ROW⁽¹⁾
0
employed a read-modify-write operation.
0 = Write Error
1 = Read Error
21:28
ECC_ERR_SYND
R/ROW⁽¹⁾
00000000
ECC Error Syndrome: Indicates the ECC syndrome value of
the most recent memory transaction in which a single-bit error
was detected. The 8-bit syndrome value indicates the data bit
position in which an error was detected and corrected.
Parity Field Bit Error: During a memory transaction an error
29
PE
R/ROW⁽¹⁾
was detected in a parity field bit.
0
0 = No parity field bit errors detected.
1 = Parity field bit error detected and corrected.
Double-Bit Error: During a memory transaction a double-bit
30
DE
R/ROW⁽¹⁾
error was detected and is not correctable.
0
0 = No double-bit errors were detected.
1 = Double-bit error was detected.
Single-Bit Error: During memory transaction a single-bit error
31
SE
R/ROW⁽¹⁾
was detected and corrected.
0
0 = No single-bit errors were detected.
1 = Single-bit error detected and corrected.
Notes:
1. ROW = Reset On Write. Any write operation to the ECCSR resets the register.
DS643 February 22, 2013
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Product Specification