DS643 Datasheet, PDF (173/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
- The second option is to push one transaction of data into the FIFOs, assert the address request on the last
data beat of the transfer, and then wait for the address acknowledge before pushing more data into the
FIFO. Waiting for the previous address acknowledge before pushing more data into the FIFO prevents
overflows. This is due to the maximum size of MPMC requests, the block RAM Write FIFO size, and the
address acknowledge behavior which is described in the next option.
• A third, more aggressive operation of the Write FIFO occupancy can be safely performed also. By relying
on the current MPMC architecture maximum of two pending transactions for a particular port, a higher
Write FIFO occupancy can be obtained. Because only two current transactions can be stored in the address
controller, the third assertion of PIM<Port_Num>_AddrAck indicates that the data associated with first
Write transaction has been completely popped from the Write FIFO. This provides space for new data in
the write FIFO that is the size of the first transaction.
Using this method, you can safely estimate the maximum current occupancy of the Write FIFO, and
throttle additional Write FIFO pushes safely below the 1024-byte limit.
Restrictions on 64-Word Burst Transfers
When using 32-bit NPI and SRL FIFOs, 64-word burst transfers are not supported because the datapath FIFOs
might not be deep enough.
If 64-word burst transfers are required with 32-bit NPI, then block RAM FIFOs must be used. All custom 32-bit NPI
PIMs should be carefully documented if they require 64-word burst transfers.
Table 92 summarizes the 64-word burst support.
Table 92: 64-Word NPI Burst Support
NPI Width
FIFO Support Support Status
64
Block RAM
Yes
64
SRL
Yes
32
Block RAM
Yes
32
SRL
No
Restrictions using Spartan-6 FPGAs
The NPI interface with the Spartan-6 FPGA MCB is limited to only one outstanding NPI transaction at a time. This
is enforced by acknowledging transactions when the data FIFO is empty.
Recommendation for Improving Write Latency
In NPI write burst transactions, the general recommendation is to perform the address request after pushing in all
the write data. The Write Data FIFO is not protected against underrun so this is the safest method of operation
because it ensures all the data is present in the Write Data FIFO before it is moved out to memory.
If reduced write latency is desired, the user can take advantage of the behavior of the MPMC control logic to know
when it is safe to make an earlier address request even though the write data for the transaction has not all been
pushed in. The user can analyze the throughput by which data is written into the FIFO and the throughput by
which the FIFO is drained out to memory to find a safe time to generate the early address request.
For example:
1. Assume the NPI width is 64 and the memory is a 32-bit DDR device. If the user design pushes in the Write data
on every NPI clock cycle, the address request can be generated immediately after the first Write data beat is
pushed in. This works because the memory datapath cannot drain the FIFO faster than it is filled.
DS643 February 22, 2013
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Product Specification