DS643 Datasheet, PDF (171/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
• When using 64-bit NPI, MPMC supports the following transfer sizes: byte, halfword, word, doubleword,
4-word cacheline, 8-word cacheline, 16-word bursts, 32-word bursts, and 64-word bursts.
• Runs only at a 1:1 clock ratio to the MPMC memory clock (PORT MPMC_Clk0); a 1:2 clock ratio is not
supported.
System design parameters are specified in the Design Parameters, page 3 and NPI Port signals are listed in PIM I/O
Signals, page 21, respectively.
It is recommended that you review the Using the MPMC in Standalone Systems, page 50 before designing a custom
PIM. For more information about using the NPI PIM, see Answer Record #24912. A link to the Answer Record is
located in the Reference Documents, page 215.
Connecting a Custom PIM to an NPI PIM
The parameters that help to connect your custom PIM to the NPI PIM are:
• C_PIM<Port_Num>_DATA_WIDTH is set to either 32 or 64. This parameter specifies the width of
PIM<Port_Num>_WrFIFO_Data and PIM<Port_Num>_RdFIFO_Data ports. The NPI data and address signals are
labeled with little-endian bit/byte ordering as illustrated in Little-Endian Memory Data Types, page 84.
• C_PIM<Port_Num>_BASETYPE must be set to NPI (4).
NPI Design Restrictions and Recommendations
The following design restrictions in the NPI PIM are described the subsequent sections:
• Restrictions on Byte, Half-Word, Word, and Doubleword Write Transfers
• Restrictions between PIM<Port_Num>_AddrReq and PIM<Port_Num>_WrFIFO_Push
• Restrictions on Pipelining of Address Requests
• Restrictions on Address Alignment
• Restrictions on SRL FIFOs
• Restrictions on Block RAM FIFOs
• Restrictions on 64-Word Burst Transfers
• Restrictions using Spartan-6 FPGAs
• Recommendation for Improving Write Latency
Restrictions on Byte, Half-Word, Word, and Doubleword Write Transfers
The address phase, write data phase, and read data phase are independent unless the MPMC is configured with the
following settings:
• C_PIM<Port_Num>_DATA_WIDTH is set to 32 and C_MEM_DATA_WIDTH is set to 32 or 64, and using DDR or
DDR2 memory.
• C_PIM<Port_Num>_DATA_WIDTH is set to 32 and C_MEM_DATA_WIDTH is set to 64 and using SDRAM.
• C_PIM<Port_Num>_DATA_WIDTH is set to 64 and C_MEM_DATA_WIDTH is set to 64, and using DDR or DDR2
memory.
• C_PIM<Port_Num>_DATA_WIDTH is set to 32 and C_MEM_DATA_WIDTH is set to 16 or 32, and using Virtex-6
FPGA DDR2 or DDR3 memory.
• C_PIM<Port_Num>_DATA_WIDTH is set to 64 and C_MEM_DATA_WIDTH is set to 32 and using Virtex-6 FPGA
DDR2 or DDR3 memory.
DS643 February 22, 2013
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171
Product Specification