DS643 Datasheet, PDF (78/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
Performance Monitor Status Register
The Performance Monitor Status register (PMSTATUS) is used to monitor the status of the clear issued to the pm
data bins. When all data bins in a PM have been cleared, the PM clear status bit is 1. This is used to ensure that the
performance monitors have been successfully cleared before enabling them. The PM clear status bit is 1 until it is
cleared by writing a 1 to toggle the bit.
Table 54 describes the PMSTATUS register bits.
Table 54: PMSTATUS Register Bit Definition
Bit(s)
Name
Core
Access
Reset
Value
0 PM0_CLR_STATUS
R/TOW
X
1 PM1_CLR_STATUS
R/TOW
X
2 PM2_CLR_STATUS
R/TOW
X
3 PM3_CLR_STATUS
R/TOW
X
4 PM4_CLR_STATUS
R/TOW
X
5 PM5_CLR_STATUS
R/TOW
X
6 PM6_CLR_STATUS
R/TOW
X
7 PM7_CLR_STATUS
8:31 Reserved
R/TOW
X
Description
1 = Data bin for PM0 is finished clearing
0 = Data bin for PM0 is not finished clearing, or clear has not been
started
1 = Data bin for PM1 is finished clearing
0 = Data bin for PM1 is not finished clearing, or clear has not been
started
1 = Data bin for PM2 is finished clearing
0 = Data bin for PM2 is not finished clearing, or clear has not been
started
1 = Data bin for PM3 is finished clearing
0 = Data bin for PM3 is not finished clearing, or clear has not been
started
1 = Data bin for PM4 is finished clearing
0 = Data bin for PM4 is not finished clearing, or clear has not been
started
1 = Data bin for PM5 is finished clearing
0 = Data bin for PM5 is not finished clearing, or clear has not been
started
1 = Data bin for PM6 is finished clearing
0 = Data bin for PM6 is not finished clearing, or clear has not been
started
1 = Data bin for PM7 is finished clearing
0 = Data bin for PM7 is not finished clearing, or clear has not been
started
Reserved
Performance Monitor Global Cycle Count Register
The Performance Monitor Global Cycle Count register (PMGCC) is a read-only 64-bit register that contains the
current value of the global cycle counter. This register is only available if the global cycle counter is enabled. Its
width can be up to 64 bits, and is padded to the left with zeros, if the counter width is smaller than 64 bits. The
PMGCC counts the total number of memory clock cycles that have elapsed because at least one PM has been
enabled. The PMGCC is a useful absolute time base of a performance monitoring session.
Performance Monitor Dead Cycle Count Register
The Performance Monitor Dead Cycle Count registers (PMx_DCC) is a read-only 64-bit register that contains the
current value of the dead cycle counter for each port.
This register is only available if the dead cycle counter has been enabled for that the port. Its width can be up to 64
bits, and is padded to the left with zeros, if the counter width is smaller than 64 bits.
Each dead cycle count represents a NPI clock cycle where a request was not immediately acknowledged by the
arbiter. This is useful to measure how many cycles a particular port has waited because performance monitoring
was first enabled.
DS643 February 22, 2013
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Product Specification