DS643 Datasheet, PDF (5/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
Table 2: System Parameters (Cont’d)
Parameter Name
C_MPMC_CTRL_P2P⁽⁶⁾
C_MPMC_CTRL_SUPPORT_BURSTS⁽⁶⁾
C_MPMC_CTRL_SMALLEST_MASTER⁽⁶⁾
Default
Value
1
0
32
C_MPMC_SW_BASEADDR
0xFFFFFFFF
C_MPMC_SW_HIGHADDR
C_NUM_IDELAYCTRL⁽⁴⁾
C_NUM_PORTS
C_PM_ENABLE
C_PM_DC_WIDTH⁽²⁾
C_PM_GC_CNTR⁽²⁾
C_PM_GC_WIDTH⁽²⁾
C_PM_SHIFT_CNT_BY⁽²⁾
0x00000000
1
1
0
48
1
48
1
C_PORT_CONFIG⁽⁸⁾
1
C_RD_DATAPATH_TML_MAX_FANOUT⁽⁷⁾
0
Allowable
Values
0,1
0,1
32, 64,128
valid address
valid address
0-16
1-8
0,1
1- 64
0,1
1- 64
0-3
0-4
0,1,2,4,8
Description
PLB v4.6 Point-To-Point (P2P) support.
PLB v4.6 PIM burst support.
PLB v4.6 smallest master on bus.
MPMC PIMs software base address used by MPMC
drivers only when
C_ALL_PIMS_SHARE_ADDRESSES=0. If not set to
valid value, the software driver uses the value from
C_PIM0_BASEADDR when
C_ALL_PIMS_SHARE_ADDRESSES=0.
MPMC PIMs software high address used by MPMC
drivers only when
C_ALL_PIMS_SHARE_ADDRESSES=0. If not set to
a valid value, the software driver uses the value
from C_PIM0_HIGHADDR when
C_ALL_PIMS_SHARE_ADDRESSES=0.
Number of IDELAYCTRL elements to instantiate.
Number of Interface Ports. MPMC GUI
automatically sets the value and places the correct
parameter in the Microprocessor Hardware
Specification (MHS) file. On Spartan-6 FPGAs, the
maximum number of ports can be limited to 6 or
less depending on the value of C_PORT_CONFIG.
Performance Monitor (PM) enable or disable:
0 = Disable
1 = Enable
Sets the width of the PM dead cycle counters
Global Clock Counter enable or disable:
0 = Disable
1 = Enable
Sets the width of the PM Global Cycle counter.
Specifies the size of the histogram bins used by the
Performance Monitors.
Spartan-6 FPGA port configuration where:
B represents bidirectional ports
U represents unidirectional ports
followed by port bit width.
0 = 6 ports (B32 B32 U32 U32 U32 U32)
1 = 4 ports (B32 B32 B32 B32)
2 = 3 ports (B64 B32 B32)
3 = 2 ports (B64 B64)
4 = 1 port (B128)
Read Database Timing Management Logic
Maximum register Fanout.
Controls the fanout of the PHY layer to the read
FIFO datapath: 0 = no register is instantiated.
1 = the read data is forwarded from the PHY to eight
sets of registers, then forwarded on to each of the
read FIFOs.
2 = the read data is forwarded from the PHY to four
sets of registers. The outputs of the registers are the
forwarded on to a maximum of two read FIFOs.
4 = the read data is forwarded from the PHY to two
sets of registers. The outputs of the registers are the
forwarded on to a maximum of four read FIFOs.
8 = the read data is forwarded from the PHY to a
single register. The output of the register is
forwarded on to a maximum of eight read FIFOs.
DS643 February 22, 2013
www.xilinx.com
5
Product Specification