DS643 Datasheet, PDF (96/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
Standalone Flow: Migrating an MPMCv5 Virtex-6 FPGA Design to MPMCv6
To migrate an existing Virtex-6 FPGA design from MPMCv5 to MPMCv6, the following actions are necessary. All
other MIG PHY types do not need special consideration to be revised.
In the UCF:
• Remove/comment the TIG constraint of the net connected to DDR3_Clk, DDR3_Clk_n, DDR2_Clk, and
DDR2_Clk_n MPMC ports:
- # NET fpga_0_DDR3_SDRAM_DDR3_Clk_pin* TIG;
- # NET fpga_0_DDR3_SDRAM_DDR3_Clk_n_pin* TIG;
• Remove _T_DCI suffix from the IOSTANDARD of the net connected to any DDR3_Clk, DDR3_Clk_n, DDR2_Clk,
and DDR2_Clk_n MPMC ports:
- NET fpga_0_DDR3_SDRAM_DDR3_Clk_pin IOSTANDARD = DIFF_SSTL15;
- NET fpga_0_DDR3_SDRAM_DDR3_Clk_n_pin IOSTANDARD = DIFF_SSTL15;
• Remove/comment the base MMCM location constraint:
- # INST */u_mmcm_clk_base LOC = MMCM_ADV_X0Y8;
• Remove/comment the OCB Monitor OLOGIC location constraint:
- # INST */gen_enable_ocb_mon.u_phy_ocb_mon_top/u_oserdes_ocb_mon LOC =
OLOGIC_X2Y130;
In the MHS file:
• On the MPMC instance, remove/comment any MPMC_Clk_Wr_I0, MPMC_Clk_Wr_O0, MPMC_Clk_Wr_I1,
MPMC_Clk_Wr_I1 ports, and connect the former driving net to a new port MPMC_Clk_Rd_Base:
- # PORT MPMC_Clk_Wr_I0 = clk_400_0000MHzMMCM0_nobuf_varphase
- PORT MPMC_Clk_Rd_Base = clk_400_0000MHzMMCM0_nobuf_varphase
• On the Clock Generator instance, remove any unused output ports/parameters due to the removal of the
MPMC write clocks of the previous step. See Virtex-6 FPGA Clock Logic, page 60 for an example.
• On the Clock Generator instance, change the C_PSDONE_GROUP parameter to MMCM0 from MMCM0_FB:
- PARAMETER C_PSDONE_GROUP = MMCM0
• On the Clock generator instance, change all C_*_VARIABLE_PHASE values to FALSE or removed, except for the
port driving the MPMC_Clk_Rd_Base signal, which must be set to TRUE.
- PARAMETER C_CLKOUT3_VARIABLE_PHASE = TRUE #MPMC_Clk_Rd_Base
MIG Spartan-3 FPGA Design Considerations
The MPMC uses the Spartan-3 FPGA PHY from MIG to implement the physical level interface for
Spartan-3/3A/3AN/3E/3A DSP devices with DDR or DDR2 memory. The MIG Spartan-3 FPGA PHYs use very
specific UCF constraints to constrain the pinout and placement of internal elements in the FPGA logic.
These constraints are specific to an individual Spartan-3 device and are not necessarily portable across devices
(even if the different devices are in the same package).
Spartan-3/3A/3AN/3E/3A DSP devices can have data width limitations depending on part and package size.
Verify data width compatibility through the MIG GUI or through the “Supported Devices” section of the
device-specific Memory Interface Solutions User Guide, in the “Spartan-3/3A/3AN/3E/3A DSP FPGA to Memory
Interfaces” section. Reference Documents, page 215 contains a link to this resource.
MIG also has guidelines for the board layout of the memory interface so that the PHY functions properly. It is
extremely important that any user boards be designed in compliance with the MIG pinout constraints and layout
guidelines for Spartan-3 FPGAs and other MIG PHY families.
DS643 February 22, 2013
www.xilinx.com
96
Product Specification