DS643 Datasheet, PDF (25/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
Table 20: NPI PIM I/O Signals (Cont’d)
Signal Name
Direction
PIM<Port_Num>_WrFIFO_Push
Input
PIM<Port_Num>_WrFIFO_Flush
Input
Write Data Phase Related Output Ports
PIM<Port_Num>_WrFIFO_Empty
Output
PIM<Port_Num>_WrFIFO_AlmostFull
Output
Read Data Phase Related Input Ports
PIM<Port_Num>_RdFIFO_Pop
Input
PIM<Port_Num>_RdFIFO_Flush
Input
Read Data Phase Related Output Ports
PIM<Port_Num>_RdFIFO_Data
Output
PIM<Port_Num>_RdFIFO_RdWdAddr
Output
Init Status
Description
This active-High signal indicates push
PIM<Port_Num>_WrFIFO_Data into write FIFOs.
Must be asserted for one cycle of MPMC_Clk0.
Cannot be asserted while PIM<Port_Num>_InitDone is 0.
x
Cannot be asserted while
PIM<Port_Num>_WrFIFO_AlmostFull is asserted.
Can be asserted before, after, or during the address phase
unless MPMC is configured in one of several special cases.
See the NPI Design Restrictions and Recommendations,
page 171.
x
Reserved. Drive with 0.
1
This active-High signal indicates that there are less than
C_MEM_DATA_WIDTH bits of data in the write FIFO.
This active-High signal indicates that
PIM<Port_Num>_WrFIFO_Push cannot be asserted on the
0
next cycle of MPMC_Clk0. This signal is only asserted when
using SRL FIFOs. If block RAM FIFOs are used, the PIM cannot
allow more than 1024 bytes of data to be pushed into the FIFOs.
This active-High signal indicates that read FIFO fetch the next
value of PIM<Port_Num>_RdFIFO_Data.
Must be asserted for one cycle of MPMC_Clk0.
Cannot be asserted while PIM<Port_Num>_InitDone is 0.
x
Cannot be asserted while PIM<Port_Num>_RdFIFO_Empty is
asserted.
See information in
PIM<Port_Num>_RdFIFO_RdFIFO_Latency to know when
PIM<Port_Num>_RdFIFO_Data is valid.
This active-High signal indicates that the read FIFO flags should
be reset. This signal must only be used when issuing commands
of PIM<Port_Num>_Size is 0x3, 0x4 or 0x5.
Must be asserted for one cycle of MPMC_Clk0.
Caution! RdFIFO_Flush must not be asserted unless
RdFIFO_Empty is 0 and there are no outstanding
acknowledged address requests.
x
If Flush asserted when multiple read address requests are
acknowledged, but where the data phases corresponding to the
address phases have not completed, MPMC is in the process of
pushing read data from the second address phase into the
FIFOs.
If the FIFO flags are reset during this time, the FIFO address
counters could obtain an unexpected value, putting MPMC in an
unstable state; risking either memory errors or the PIM going into
a state of deadlock.
Data to be popped out of MPMC read FIFOs.
Only valid a certain number of cycles after
0
PIM<Port_Num>_RdFIFO_Push is asserted, and/or
PIM<Port_Num>_RdFIFO_Empty is deasserted, as specified
by PIM<Port_Num>_RdFIFO_Latency.
Data is little-endian as shown in Figure 7, page 84.
Indicates the word of a cache line transfer to which
PIM<Port_Num>_RdFIFO_Data corresponds.
0
Only valid a certain number of cycles after
PIM<Port_Num>_RdFIFO_Push is asserted,
as specified by PIM<Port_Num>_RdFIFO_Latency.
Counts by 1 with a 32-bit NPI; counts by 2 with a 64-bit NPI.
DS643 February 22, 2013
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Product Specification