DS643 Datasheet, PDF (17/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
Table 11: System I/O Signals (Cont’d)
Signal Name
MPMC_Idelayctrl_Rdy_I⁽¹⁾
MPMC_Idelayctrl_Rdy_0⁽¹⁾
MPMC_InitDone
MPMC_PLL_Lock⁽³⁾
selfrefresh_enter⁽³⁾
selfrefresh_mode⁽³⁾
Direction
Input
Output
Output
Input
Input
Output
Init Status
Description
Automatically This active-High input is combined with internal IDELAYCTRL
set to 1 if instance(s) RDY signal(s) to indicate that the memory initialization
unconnected can begin.
This active-High output indicates that the internal IDELAYCTRL
0
instance(s) RDY signal(s) and the MPMC_Idelayctrl_Rdy_I are
all High.
This active-High signal, when asserted, indicates that the memory
0
initialization has completed successfully. When Low, the memory is
currently being calibrated and configured.
x
Lock signal from PLL driving clocks to MCB.
Automatically
set to 0 if Reserved - Not supported MCB feature.
unconnected
0
Reserved - Not supported MCB feature.
Notes:
1. Signals are applicable MIG-based Virtex-4/Virtex-5/Virtex-6 FPGA PHY only.
2. Signals are applicable when using Static PHY only. This includes the SDRAM PHY. Also used by the Virtex-6 FPGA MIG PHY.
3. Spartan-6 FPGAs only.
4. Virtex-6 FPGAs only.
Memory Signals
SDRAM PHY I /O Signals (Spartan-3, Virtex-4, and Virtex-5 FPGAs Only)
Table 12: SDRAM PHY I/O Signals
Signal
SDRAM_Addr
SDRAM_BankAddr
SDRAM_CAS_n
SDRAM_CE
SDRAM_Clk
SDRAM_CS_n
SDRAM_DM
SDRAM_DQ⁽¹⁾
SDRAM_RAS_n
SDRAM_WE_n
Direction
Output
Output
Output
Output
Output
Output
Output
In/Out
Output
Output
Init Status
Description
x
Row/Column address.
x
Bank address.
1
Command input.
0
Clock enable (memory CKE signal.)
0
Clock to memory.
1
Chip select, active-Low.
0
Data masks.
z
Data bits.
1
Command input.
1
Command input.
Notes:
1. The MHS signal connecting this port and the MHS external port must have the same name. See
www.xilinx.com/support/answers/14264.htm.
DS643 February 22, 2013
www.xilinx.com
17
Product Specification