DS643 Datasheet, PDF (144/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
X-Ref Target - Figure 26
CHNL_CTRL.IRQCount
[(Link_EOF And not (CHNL_CTRLUseIntOnEnd)
OR
(STS_CTRL_APP0.IntOnEnd AND CHNL_CTRL.UseIntOnEnd)]
AND
Descriptor_Updated
AND
PI_WrFIFO_Empty
CHNL_CTRLLdrIRQCnt
OR
(Timer_Int AND CHNL_CTRIrqDlyEn)
OR
Coal_Int
D
Decr
Load
Coal_int
=0
Incr
Decr
Coal_int
0
IRQ_REQ_WE AND IRQ_REG.CoaIRQ
Figure 26: Coalescing Counter Interrupt Scheme
DS643_27_071307
In this example:
• Upon reset, the CHNL_CTRL.IRQC count value is used to load the coalescing counter. Subsequently, the register
field, TxIrqCountReg[0:7], can be programmed with any 8-bit value.
• On every EOP or irq-on-end (selected by CHNL_CTRL_UseIntOnEnd), the counter decreases. When the
coalescing counter reaches 0, the DMA increases the 4-bit interrupt counter.
• When the 4-bit interrupt counter is non-zero, it generates an interrupt to the CPU (if the irq_enable bit of the
respective channel is set).
• When the interrupt is acknowledged (with a control register write value of 1), the 4-bit interrupt counter is
decreases.
• The contents of the TxIrqCountReg[0:7] register is reloaded when the 4-bit interrupt counter increases.
There is also a means provided for the CPU to force the counter to load the contents of the TxIrqCountReg[0:7]
register. This is achieved when the CPU writes the ldIrqCnt field.
Note: When the delay timer fires, the Coalescing Counter automatically reloads automatically.
SDMA Engine Reset
It is possible to reset a particular SDMA engine (both Rx and Tx channels simultaneously) whenever a “lockup”
situation arises or an error is detected.
The software reset bit, DMA_CONTROL_REG.SwReset allows the software application to reset SDMA. When you
write a 1 to DMA_CONTROL_REG.SwReset, it initiates the reset sequence for that SDMA. At the same time, the
SDMA_RstOut output is asserted, synchronous to the LocalLink clock. This output can be used as an external logic
reset.
After a soft reset is initiated, software must poll the DMA_CONTROL_REG.SwReset bit until it is sampled as
deasserted, which indicates that the reset sequence is complete and the pipeline is flushed. Simultaneously with the
DMA_CONTROL_REG.SwReset bit being cleared, the SDMA_RstOut is deasserted automatically.
Note: When the DMA engine reset function is used, there is no guarantee that the current descriptor completed correctly. The
assumption should be that the descriptor did not complete and it should be restarted again using the normal CPU technique for
starting a new DMA operation.
DS643 February 22, 2013
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Product Specification