DS643 Datasheet, PDF (153/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
Table 78: Channel Status Register (Cont’d)
Bit(s)
Name
Core Reset
Access Value
Description
16:23 Reserved
Reserved - Read as zero.
24
Error
Read
0
DMA Error: This bit indicates that an error occurred during DMA operations. This bit is an
OR’ing of error bits 10 to 15.
25
IOE
Read
0
Interrupt On End: This bit is a copy of the corresponding bit in the STS_CTRL_APP0 field
of the descriptor.
26
SOE
Read
0
Stop On End: This bit is a copy of the corresponding bit in the STS_CTRL_APP0 field of
the descriptor.
27
Cmplt
Read
0
Complete: When set indicates that the DMA has transferred all data defined by the current
descriptor.
28
SOP
Read
Start of Packet (SOP): For transmit, the CPU sets this bit in the descriptor to indicate that
0
this is the first descriptor of a packet to be transmitted. For Receive, this bit being set
indicates that a valid SOP was received on the LocalLink side.
29
EOP
Read
End of Packet (EOP): For Transmit, the CPU sets this bit in the descriptor to indicate that
0
this is the last descriptor of a packet to be transmitted.
For Receive, this bit being set indicates that a valid EOP was received on the LocalLink
side.
30
EngBusy
Read
Engine Busy: When set, indicates that the respective channel is busy with a DMA
0
operation.
Generally, software should not write any DMA registers while this bit is set. Reading of
registers is allowed.
31
Reserved
Read
Reserved - Read as zero.
DMA Control Register
Offset: 0x40
The DMA Control register controls the DMA operation. Figure 36 illustrates the DMA Control register, and Table 79
describes the DMA Control register bits.
X-Ref Target - Figure 36
Reserved
‘1’ ‘1’ SwReset
0
26 27 28 29 30 31
Figure 36: DMA Control Register
‘1’ ^Rsvd
DS643_17_071307
Table 79: DMA Control Register
Bit(s)
Name
Core
Access
0:26
Reserved
27
Reserved
28
Reserved
29
Reserved
30
Reserved
31
SwReset
Read/Write
Reset
Value
0
1
1
1
0
0
Description
Reserved - read as zero
Reserved - read as one
Reserved - read as one
Reserved - read as one
Reserved - read as zero
Software Reset
Writing a 1 to this field forces the DMA engine to shutdown and reset itself.
After setting this bit, software must poll it until the bit is cleared by the DMA.
This indicates that the reset process is done and the pipeline has been
flushed
1= Reset DMA - Resets both Rx and Tx Channels
0= Normal Operation (default)
DS643 February 22, 2013
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Product Specification