DS643 Datasheet, PDF (192/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
• Match PHY SDR datapath width to NPI data width. The SDR datapath width of the PHY is 1x the memory
width for SDRAM and 2x the memory width for DDR/DDR2. The NPI width of some PIMs can be selected
between 32 and 64 bits. Designing the system so that the PIM NPI width and the PHY SDR datapath widths
match optimize the flow of data and reduce logic utilization.
For example, if a system has a 16-bit DDR and uses PLB PIMs, the PLB PIM should be configured to have an
NPI width of 32 bits to minimize MPMC size (Parameter C_SPLB<Port_Num>_NATIVE_DWIDTH = 32). If the
default NPI width of 64 bits is used instead, wider datapath FIFOs and datapath switches are generated causing
more logic to be used.
VFBC, NPI, and PLB v4.6 PIMs all have user configurable NPI data widths. The SDMA PIM is fixed to a 64-bit
NPI data width and the XCL PIM is fixed to a 32-bit NPI width. See the Personality Interface Module (PIM)
Parameters, page 13 for more information.
In PowerPC 405 processor systems, the IPLB0 and DPLB0 ports can be combined using a PLB arbiter to connect
to a single MPMC port (see “Standard PowerPC 405 Processor CoreConnect Use Case, page 47 for an example.)
This reduces MPMC size compared to a two-port MPMC with separate PLB PIMs connected to IPLB1 and
DPLB1 with system performance as the trade-off.
• In MicroBlaze processor systems, cached memory access travels over IXCL and DXCL ports to two separate
MPMC XCL ports. By default, uncached access to memory travels over the PLB port to a third MPMC PLB
port. This approach uses three MPMC ports per MicroBlaze processor. To save logic resources, the MicroBlaze
processor could be configured with parameter C_ICACHE_ALWAYS_USED = 1 and C_DCACHE_ALWAYS_USED
= 1 so that uncached memory access flows over the XCL ports. This allows the third MPMC port to be
removed to reduce system size.
• The MicroBlaze processor IXCL and DXCL ports can be connected to a dual XCL PIM which uses only one
MPMC port for two XCL connections. Using the dual XCL PIM significantly reduces MPMC size.
• Using a fixed priority arbiter (Parameter C_ARB0_ALGO = FIXED) saves some logic over a round robin arbiter
and is a significant savings over a custom arbitration setting.
• Using STATIC PHY over MIG PHY also reduces logic utilization because the static PHY is more simple in
structure; however, the static PHY is also less robust than the MIG PHY and is therefore not recommended. See
Configurable Physical Interface, page 81 for more information.
• Disabling optional pipeline stages in the MPMC reduces flip-flop utilization but also degrades timing.
• Minimize the number of ports or set ports to be read-only or write-only when possible.
Note: Ports with C_PIM<Port_Num>_SUBTYPE set to “IXCL” and “IPLB” are automatically configured to be read-only.
Timing Optimization
The following list identifies possible ways to improve timing of MPMC systems:
• Generally, the size optimizations detailed in MPMC Size Optimization, page 191 reduce MPMC complexity
and improve timing (except removal of pipeline stages.)
• Better matching of datapath widths between PHY and PIMs also improves timing because it minimizes
MUXes used for width matching logic. For example, a 16-bit DDR memory has an internal 32-bit PHY
datapath. This would better match with a 32-bit NPI interface than a 64-bit NPI interface.
• Experiment with different values for C_RD_DATAPATH_TML_MAX_FANOUT. All other pipeline stages are turned
on by default. Keeping the pipeline stages enabled improves timing and Fmax.
• Minimize the use of DCMs to synthesize the MPMC memory and PIM clocks. If possible the board should
provide a clock source that directly inputs the desired MPMC memory clock frequency. Using on-chip clock
synthesis and cascading of DCMs can increase clock jitter which degrades the timing budget of the overall
system.
• MPMC timing can be greatly affected by block RAM placement. The use of block RAM floorplanning can
greatly improve MPMC timing results. If the number of available block RAMs in a design is low, freeing up
block RAM can improve timing. This is especially important on Virtex-5 FPGA designs. Choosing the memory
interface DQ pinout so they are placed near columns of block RAMs might also improve timing.
DS643 February 22, 2013
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