DS643 Datasheet, PDF (150/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
Table 73: Current Buffer Length Register Description
Bit(s)
Name
Core
Access
Reset Value
Description
TX_CURBUF_LENGTH
0:31 and
RX_CURBUF_LENGTH
Read
0x00000000 Length in bytes of the current buffer being processed by SDMA.
Current Descriptor Pointer (TX_CURDESC_PTR, RX_CURDESC_PTR)
Offsets: 0x0C and 0x2C
The Current Descriptor Pointer register, one for transmit and one for receive, maintains the pointer to the buffer
descriptor that is currently being processed. The value was set either by the CPU when it first initiated a DMA
operation, or is copied from the Next Descriptor Pointer register upon completion of the prior descriptor. This value
is maintained by the SDMA as a pointer so that the SDMA can update the status and application dependent fields
of the descriptor after the buffer descriptor has been fully processed. Table 74 describes the Current Descriptor
Pointer register bits.
Table 74: Current Descriptor Pointer Register Description
Bit(s)
Name
Core Access Reset Value
Description
0:31
TX_CURDESC_PTR
and
RX_CURDESC_PTR
Read/Write
0x00000000
An 8-word aligned pointer to the current buffer descriptor being
processed by the SDMA.
Tail Descriptor Pointer (TX_TAILDESC_PTR and RX_TAILDESC_PTR)
Offsets: 0x10 and 0x30
The Tail Descriptor Pointer register, one for transmit and one for receive, maintains the pointer to the buffer
descriptor chain tail. Tail Pointer Mode is always enabled; consequently, DMA operations halt when processing of
the buffer descriptor pointed to by TAILDESC_PTR is completed. Writing to this register starts DMA operations.
Table 75 describes the Tail Descriptor Pointer register bits.
Table 75: Tail Descriptor Pointer Register Description
Bit(s)
Name
Core
Access
Reset Value
Description
0:31
TX_TAILDESC_PTR
and
RX_TAILDESC_PTR
Read/Write
0x00000000
An 8-word aligned pointer to the tail descriptor. The software
application writes to this field to initiate a DMA transfer.
Channel Control Register (TX_CHNL_CTRL and RX_CHNL_CTRL)
Offsets: 0x14 and 0x34
The Channel Control register, one for transmit and one for receive, controls interrupt processing for the particular
channel. Figure 33 illustrates the Channel Control register, and Table 76 describes the Channel Control register bits.
X-Ref Target - Figure 33
IrqErrEn
IrqErrEn
Reserved
LdlRQCnt Reserved IrqCoalEn
0
78
15 16
20 21 22 23 24 25
28 29 30 31
IRQTimeout
IRQCount
IrqEn
UseIntOnEnd
Figure 33: Channel Control Register
IrqDlyEn
DS643_14_071307
DS643 February 22, 2013
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