DS643 Datasheet, PDF (65/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
X-Ref Target - Figure 6
ECC Control/Status
Registers
Data Path
Read FIFO(s)
NPI
Write
NPI
FIFO(s)
BRAM Read
Data FIFO
(for Read-Modify-Write,
same width as SDR
data from PHY)
Byte Wide Muxes
(for Read-Modify-Write,
Provides read data for
masked off bytes
during writes)
Byte Enable/
0
Mask Data
ECC Error
Detection/Correction
Status
DOut
16/32/64/128
Bits Wide
DIn
PHY Interface
SDR Read
Data
DDR/DDR2
Data
ECC Check Bit
Encode 8/16/32/64/128
Bits Wide
DIn DOut
ECC
DOut
SDR Write
Data
SDR ECC
Write Data
SDR Mask
Data
8/16/32/64
Bits Wide
ECC
Parity
8
Bits Wide
X10919
Figure 6: Data Path with ECC Enabled
When ECC functionality is enabled, several blocks are turned on to implement control and status registers, ECC
decode and encode, and support for Read-Modify-Write (RMW) operations (needed for handling byte enables).
Note: All writes are RMW in the MPMC core after ECC is enabled.
The blocks are inserted between the PHY and datapath so only one instance of the ECC logic is needed for multiple
port configurations. The ECC decode and encode is performed in the SDR domain. The ECC Control and Status
registers module controls when interrupts are generated and provides control and status data access with respect to
ECC. See Common MIG PHY Debug Registers, page 34 for more information on ECC Control and Status registers.
After each start-up or MPMC reset the entire memory must be initialized when using ECC. Typically this is
performed by user software. The following steps should be performed to initialize external memory for ECC use:
1. Disable ECC interrupt registers.
2. Enable Read/Write ECC support.
3. Clear values of all external memory addresses.
4. Clear ECC error count registers.
5. Enable ECC interrupts.
Note: ECC interrupts must be disabled for the initialization process. Because the external ECC check bits are uninitialized,
Read and RMW transactions to external memory could cause ECC errors. These errors generate spurious ECC interrupts to the
processor, potentially causing system hangs.
DS643 February 22, 2013
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Product Specification