DS643 Datasheet, PDF (159/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
Table 83: Required PPC440 Block MI_CONTROL/C_PPC440MC_CONTROL Register Settings
Bit(s)
Name
Required
Value
Setting
Description
0
enable
1
Turn on the PPC440MC interface.
1
Rowconflictholdenable
0
PPC440MC PIM does not support row/bank management.
2
Bankconflictholdenable
0
PPC440MC PIM does not support row/bank management.
3
Directionconflictholdenable
0
PPC440MC PIM does not support row/bank management.
4:5
Autoholdduration
00
PPC440MC PIM only supports this autohold mode.
6
2:3 Clock Ratio mode
0
PPC440MC PIM only supports integer clock ratios. It does not support a
clock ratio of 2:3 with respect to CPMINTERCONNECTCLK.
7
overlaprddwr
0
Overlapped transfers and QDR mode are not supported.
8:9
Burstwidth
Depends on
memory type
and width
See Table 84, page 161 for supported values. The range of allowable values
depend upon memory type and width.
10:11
Burstlength
Depends on
memory type
and width
See Table 84 for supported values. The range of allowable values depend
on memory type and width.
12:15
Write Data Delay (WDD)
0000
PPC440MC PIM supports this WDD mode only.
16
RMW
0
PPC440MC PIM supports this setting only.
17:23 Reserved
0000000 Reserved
24
PLB Priority Enable
0, 1
1 = Default BSB selection.
0 = SPLB ports PLB Mn_Priority is not used for arbitration.
25:27 Reserved
000
Reserved
28
Pipelined Read Enable
1 = default BSB selection which allows multiple read commands to be
0, 1
accepted.
0 = multiple read commands are not accepted.
29
Pipelined Write Enable
1 = default BSB selection which allows multiple write commands to be
0, 1
accepted.
0 = multiple write commands are not accepted.
30:31 Reserved
11
Reserved
All bits not shown in Table 81, page 156 can normally be set by the users as described in the Embedded Processor
Block in the Virtex-5 FPGA Reference Guide (a link to this document is provided in Reference Documents, page 215).
PPC440MC Overview
The PPC440MC PIM is the interface between the NPI and the PowerPC 440 processor memory interface block, as
shown in Figure 37.
DS643 February 22, 2013
www.xilinx.com
159
Product Specification