DS643 Datasheet, PDF (157/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
• 64-Bit Single PIM
• Single word Read and Write transactions (reduced size when burst support is not needed)
• 32-Bit Single PIM
• Single word Read and Write transactions (reduced size when burst support is not needed)
• DPLB
• Single word Read and Write transactions; and 8-word, cacheline Read and Write transactions
• IPLB
• 4-word and 8-word, cacheline Read transactions
Caution! When choosing a SUBTYPE, be sure the SUBTYPE supports all the PLB transaction types that are issued to the
PLB v4.6 PIM. When an unsupported transaction is issued on the PLB bus, it is possible to cause the logic in the PLBv4.6
PIM to hang, which would require a system reset to recover.
Supported Transactions by SUBTYPE
The supported transactions for each of the SUBTYPES are listed in Table 82.
Table 82: Supported Transactions
SPLB_PLB_SIZE
[0:3]
Description Read/Write
SPLB_PLB_SIZE (0:3)
SPLB_PLB_SIZE[0:3]
Read
0x0
Single Transactions
Write
Read
0x1
4-wd Cacheline
Write
Read
0x2
8-wd Cacheline
Write
Read
0x3
16-wd Cacheline
Write
0x4
Reserved
Read
Write
0x6
Reserved
Read
Write
0x7
Reserved
Read
Write
0x8
Byte Bursts
Read
Write
Read
0x9
Halfword Bursts
Write
0xA
Word Bursts
Read
Write
Read
0xB
Doubleword Bursts
Write
Read
0xC
Quad Word Bursts
Write
Read
0xD
Octal Word Bursts
Write
0xE
Reserved
Read
Write
0xF
Reserved
Read
Write
C_PIM<Port_Num>_SUBTYPE
PLB DPLB IPLB Single
Y
Y
N
Y
Y
Y
N
Y
Y
N
Y
N
Y
N
Y
N
Y
Y
Y
N
Y
Y
Y
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
Y
N
N
N
Y
N
N
N
Y
N
N
N
Y
N
N
N
Y
N
N
N
Y
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
DS643 February 22, 2013
www.xilinx.com
157
Product Specification