DS643 Datasheet, PDF (121/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
Personality Interface Modules
The Personality Interface Module (PIM) architecture comprises the following interfaces:
• Xilinx CacheLink PIM
• Soft Direct Memory Access Controller PIM for LocalLink Interfaces
• Processor Local Bus Version 4.6 PIM
• PowerPC 440 Processor Memory Controller PIM
• Video Frame Buffer Controller PIM
• Native Port Interface PIM
• MCB PIM
PIM Base/High/Offset Parameters
Each PIM supports PIM-specific Base/High/Offset address parameters. The Base/High/Offset parameters are
defined as a 32-bit value of C_<PIM_Type>_[BASEADDR|HIGHADDR|OFFSET]. The value set in the
C_ALL_PIMS_SHARE_ADDRESSES parameter determines if all ports have a common base and high address or if
each port has independently-configured memory address ranges. If you want to implement a shadow or aliased
memory you need to double the amount of addressable memory. This can be done by increasing the
C_<PIM_Type>_HIGHADDR by an amount that doubles the address range. MPMC supports a maximum of
2 gigabytes total memory.
The following subsections describe the PIMs. The PIM design parameters, I/O signals, and control and status
register summaries are in Design Parameters, page 3, I/O Signals, page 16, and Control and Status Registers,
page 32, respectively.
Note: Throughout the document, the size of a word is 32 bits.
Xilinx CacheLink PIM
The Xilinx CacheLink (XCL) PIM allows connection from an XCL bus interface to the MPMC. The XCL PIM is
described in the following subsections:
• XCL Features
• XCL Overview
• Connecting XCL to a MicroBlaze Processor
• XCL Configuration Options
• XCL Line Size and Write Transfers
• XCL Pipeline Stages
• XCL Clock Requirements
• XCL Additional Information
DS643 February 22, 2013
www.xilinx.com
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Product Specification