DS643 Datasheet, PDF (105/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
This clock phase relationship makes the SDR data appear misaligned with respect to the pairs of DDR data from
memory. In this case, half of the data appears on the first posedge of MPMC_0_Clk0, and half of the data appears
on the second posedge of MPMC_Clk0. This stage is not present for SDRAM designs.
A multiplexor (MUX) lets you correct for the misalignment by selecting how the DDR data should be arranged
into SDR data. The default value of the MUX is controlled by the C_STATIC_PHY_RDDATA_SWAP_RISE
parameter. You can change this value using the software interface at a later time, if required.
4. The last part of the Static PHY consists of a shift register that can adjust the delay of the read enable signal to the
datapath (which causes read data to be pushed into the read FIFO).
Depending on the parameter settings, clock frequency, and board layout, the read data to the datapath might
appear on a different clock cycle relative to the read enable signal from the control path.
The control path sends a read enable to the PHY at the same time that it sends the read command to the PHY.
The PHY then must delay this signal for a certain number of cycles to make the read FIFO push signal valid at
the same time as the data coming out of the Static PHY.
The C_STATIC_PHY_RDEN_DELAY parameter sets the default value for this delay. You can change this value
using the software interface at a later time, if required.
If this parameter is set incorrectly, and a read is performed, it is possible that the read data is pushed into a
different FIFO than where the data was intended. This typically occurs only if the read was not issued on port
0. If the data is pushed into the wrong FIFO, the result can be identified by a processor hang that can be
recovered from by resetting the system only. The correct setting for this parameter depends on MPMC pipeline
configurations, clock frequency, and board layout, but typically this parameter is set to 5, 6, or 7 for DDR and
DDR2; and 4, 5, or 6 for SDRAM.
Additionally, if you are generating the MPMC_Clk_Mem with a DCM that is enabled to use variable phase shift,
the Static PHY Control register interface provides an easy way to control the PSEN and PSINCDEC ports of the
DCM.
The MPMC provides a control port that can be connected to a DCM control port. This allows you to control the
DCM phase adjust through the MPMC control registers. See the Static PHY Interface Register, page 107 for
more details.
Static PHY Implementation Considerations
The important implementation considerations when using the Static PHY are:
• Control Register Values
• Timing Constraints
• DCM Phase Adjust Port
• Matching Delay Traces
The following subsections detail the implementation considerations.
Control Register Values
If you already know the control register values needed for the Static PHY to work with your board and this value
is stable, you can choose to fix these values so that the PHY operates correctly upon power-on. You can do this by
setting the DCM phase adjust and parameters values for C_STATIC_PHY_RDDATA_CLK_SEL,
C_STATIC_PHY_RDDATA_SWAP_RISE, and C_STATIC_PHY_RDEN_DELAY as necessary.
Timing Constraints
When using the Static PHY, timing constraints are needed; you must set the UCF constraints to ensure that the
maximum delay for data signals passing from MPMC_Clk_Mem to MPMC_Clk0 clock domains is 1/2 the period of
MPMC_Clk0. The following is an example of such a timing constraint where no dynamic DCM phase adjustment is
used:
DS643 February 22, 2013
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105
Product Specification