DS643 Datasheet, PDF (15/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
Table 7: SDMA PIM Design Parameters (Cont’d)
Parameter Name
C_SDMA<Port_Num>_PRESCALAR⁽¹⁾
C_SDMA<Port_Num>_PI2LL_CLK_RATIO⁽¹⁾
C_SDMA<Port_Num>_COMPLETED_ERR_TX⁽¹⁾
C_SDMA<Port_Num>_COMPLETED_ERR_RX⁽¹⁾
Default Value
100
1
1
1
Allowable
Values
0-1023
1,2
0,1
0,1
Description
Interrupt Delay Timer Scale Factor.
NPI to LocalLink Clock ratio.
Transmit complete with error checking.
0 = Disable complete bit error checking.
1 = Enable complete bit error checking.
Receive complete with error checking.
0 = Disable complete bit error checking.
1 = Enable complete bit error checking.
Notes:
1. Valid if C_PIM<Port_Num>_BASETYPE = 3 (SDMA).
2. If C_ALL_PIMS_USED_SHARED_ADDRESS is 1, there is one common BASEADDR/HIGHADDR for all SDMAs
(C_SDMA_CTRL_BASEADDR); otherwise, each SDMA Port has a unique BASE/HIGHADDR (C_SDMA_CTRL<Port_Num>_BASEADDR).
3. These parameters are normally calculated by the XPS based on what devices are connected to the PLB bus.
NPI PIM Design Parameters
Table 8 lists the NPI PIM design parameters.
Table 8: NPI PIM Design Parameters
Parameter Name
Default
Value
C_PIM<Port_Num>_DATA_WIDTH
64
Allowable
Values
32,64
Description
PIM Native Data Width.
MIB/PPC440MC PIM Design Parameters
Table 9 lists the MIB/PPC440MC PIM design parameters.
Table 9: MIB/PPC440MC Design Parameters
Parameter Name
Default
Value
C_PPC440MC<Port_Num>_BURST_LENGTH
4
C_PPC440MC<Port_Num>_PIPE_STAGES
1
Allowable
Values
2,4,8
0-2
Description
Length of allowable bursts.
Number of pipeline stages to insert.
VFBC PIM Design Parameters
Table 10 lists the VFBC PIM design parameters.
Table 10: VFBC PIM Design Parameters
Parameter Name
C_VFBC<Port_Num>_ CMD_FIFO_DEPTH
C_VFBC<Port_Num>_CMD_AFULL_COUNT
C_VFBC<Port_Num>_RDWD_FIFO_DEPTH
C_VFBC<Port_Num>_RDWD_DATA_WIDTH
C_VFBC<Port_Num>_
RD_AEMPTY_WD_AFULL_COUNT
Default
Value
32
3
1024
32
3
Allowable Values
Description
32,64,128,256,512,1024,2048,
4096,8192⁽¹⁾
Depth of the command FIFO in 32-bit words.
0 - C_VFBC<Port_Num>_
CMD_FIFO_DEPTH
Command FIFO almost full threshold.
512,1024,2048,
4096, 8192⁽¹⁾
Read/Write FIFO depth in the number of
data words (word size is defined by the
RDWD_DATA_WIDTH parameter.)
8,16,32,64
Data width in number of bits.
0 - C_VFBC<Port_Num>_ Write FIFO Almost Full Threshold and Read
RDWD_FIFO_DEPTH
FIFO Almost Empty Threshold.
Notes:
1. As the FIFO depth for each FIFO is increased, the FIFO consumes more block RAMs. The upper limit is constrained by the number of block
RAMs available on the FPGA and the number of block RAMs used.
DS643 February 22, 2013
www.xilinx.com
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Product Specification