DS643 Datasheet, PDF (91/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
MIG/MPMC Tool Flow
This section outlines the MPMC to MIG tool flow. MIG is a tool that is delivered within the CORE Generator™ tool.
There are two options for using MIG with the MPMC:
• Integrated MIG GUI Flow
• Standalone MIG GUI Flow
The integrated flow manages the MIG project automatically and is therefore recommended. The standalone flow
provides a more manual flow for converting a MIG pinout into the MPMC. The following subsections describe the
options.
Integrated MIG GUI Flow
The Integrated MIG GUI flow offers a simplified method for working with the MIG GUI to generate a memory
interface pinout and constraint file. It is available for Spartan-3, Virtex-4, Virtex-5, or Virtex-6 FPGA designs only. In
this flow, the MIG GUI is invoked from within the MPMC GUI and the output of the MIG tool is imported and
managed automatically by EDK. This flow has fewer steps for running MIG to generate MPMC pinouts and
constraints within the XPS GUI. The integrated flow seeds the CORE Generator system project files and the MIG
GUI project files automatically and eliminates some of the option screens from within the MIG GUI by inferring
them from the MPMC settings.
The disadvantage of this flow is that it reduces visibility into the tool interactions which can make debugging,
handling special cases, or workarounds more difficult to implement. A prime example of this disadvantage can be
encountered when specifying the number of pins that are used to drive Clock/ODT/CE/CSn. The interface
between the MPMC and MIG tool models each memory as components, rather than DIMMs. The MIG tool might
require a pin be specified for each separate component (eight components if using x8 parts in a DIMM.) To continue
through the tool, dummy pins should be assigned and the correct number of pins should be specified in the MPMC
GUI. The extra pins are pruned away. Alternatively, if MIG does not allow you to specify as many pins as you
would like, then the extra pins should be assigned a LOC constraint in the EDK system UCF. This flow is
recommended for new designs. For designs with existing MPMC and MIG projects built under the previous
Standalone MIG GUI Flow, it is recommended that the standalone flow continue to be used although you can use
the integrated flow to update an older MIG project.
Note: BSB MPMC designs use the standalone flow for handling the MPMC UCF constraints.
The following steps describe the integrated flow. See the device-specific Memory Interface Solution User Guide for
more information on options in the MIG GUI.
1. Ensure that you have installed the CORE Generator tool and any available updates. Although the CORE
Generator tool is not invoked in GUI mode, the tool is executed at the command line by underlying scripts.
2. Using the MPMC IP configuration GUI, configure MPMC for you application. This process is described in IP
Configuration Graphical User Interface, page 209.
3. Configure the MPMC as needed; ensure the Memory Interface tab has all the memory information.
4. Click the MIG Settings tab, and check the USE Integrated MIG GUI Flow box to enable the integrated MIG GUI
flow. This allows the Launch MIG button to be active; click this button to open MIG.
5. In the MIG Output Options window, select Create Design > Next.
6. In the MIG Pin Compatible FPGAs window, check any other devices that the pinout must use to be
compatible, then click Next.
7. In the MIG FPGA Options and Extended FPGA Options windows, make the appropriate selections, then
click Next.
a. The selection of Single Ended or Differential System Clock does not affect the MPMC.
DS643 February 22, 2013
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Product Specification