DS643 Datasheet, PDF (70/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
ECC Single-Bit Error Count Register
The ECC Single-Bit Error Count register (ECCSEC) records the number of ECC single-bit errors that occurred
during the memory transaction on the data bits only. When using the force error feature, the number of errors
detected might not be as expected because the force error feature counts the number of memory data beats that have
errors, not the number of NPI data beats that have errors. Because the Read_Modify_Write might read more data
than NPI requested, the count can be misleading. The ECC logic corrects the detected single-bit errors. When the
value in this register reaches 4095 (the max count), the next single-bit error detected is not counted. This count
consumes 12 bits.
Note: Single bit errors occurring on ECC check bits are covered by the ECCPEC register.
Table 45 describes the bit values for the ECC Single-Bit Error Count register.
Table 45: ECCSEC Bit Definitions
Bit(s)
Name
Core Reset
Access Value
Description
0:19
Reserved
20:31
SEC R/ROW⁽¹⁾
Single-Bit Error Count. Indicates the number of single-bit errors that
0 occurred during the previous memory transactions. The maximum error
count is 4095.
Notes:
1. ROW = Reset On Write. Any write operation to the ECCSEC register resets the register.
ECC Double-Bit Error Count Register
The ECC Double-Bit Error Count register (ECCDEC) records the number of ECC double-bit errors that occurred
during the memory transaction. ECC cannot correct double-bit errors detected. When the value in this register
reaches 4095 (the max count), the next double-bit error detected is not counted. When using the force error feature,
the number of errors detected might not be as expected because the force error feature counts the number of
memory data beats that have errors, not the number of NPI data beats that have errors.
Table 46 describes the bit values for the ECCDEC.
Table 46: ECCDEC Bit Definitions
Bit(s)
Name
Core
Access
Reset
Value
Description
0:19
Reserved
20:31t
DEC R/ROW⁽¹⁾
Double-Bit Error Count: Indicates the number of double-bit
0
errors that occurred during the previous memory transactions.
The maximum error count is 4095.
Notes:
1. ROW = Reset On Write. Any write operation to the ECCDEC register resets the register.
DS643 February 22, 2013
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Product Specification