DS643 Datasheet, PDF (12/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
Per-Port Parameters
Table 4 lists the per-port parameters. These are valid for Spartan-6 FPGAs only.
Table 4: Per-Port Parameters
I/O Signal Name
C_PIM<Port_Num>_BASETYPE⁽⁴⁾
Default
Value
2 (Port 0)
0 (Ports 1-7)
C_PIM<Port_Num>_SUBTYPE
x
C_PIM<Port_Num>_B_SUBTYPE⁽⁹⁾
x
C_PIM<Port_Num>_BASEADDR^(1),(7)
C_PIM<Port_Num>_HIGHADDR^(1),(8)
C_PIM<Port_Num>_OFFSET⁽¹⁾
C_PI<Port_Num>_RD_FIFO_TYPE⁽¹¹⁾
0xFFFFFFFF
0x00000000
0x00000000
BRAM
C_PI<Port_Num>_WR_FIFO_TYPE^(6),(11)
C_PI<Port_Num>_ADDRACK_PIPELINE^(3),(10)
C_PI<Port_Num>_RD_FIFO_APP_PIPELINE⁽¹⁰⁾
C_PI<Port_Num>_RD_FIFO_MEM_PIPELINE^(4),(10)
C_PI<Port_Num>_WR_FIFO_APP_PIPELINE⁽¹⁰⁾
C_PI<Port_Num>_WR_FIFO_MEM_PIPELINE^(5),(10)
C_PI<Port_Num>_PM_USED^(2),(3),(10)
BRAM
1
1
1
1
1
1
Allowable
Values
0-9
DXCL, DXCL2,
IXCL, IXCL2,
XCL, IPLB,
DPLB, PLB,
SDMA, NPI,
PPC440MC,
VFBC, MCB,
INACTIVE
DXCL, DXCL2,
IXCL, IXCL2,
XCL
Valid Address
Valid Address
Valid Address
BRAM, SRL,
DISABLED
BRAM, SRL,
DISABLED
0,1
0,1
0,1
0,1
0,1
0,1
Description
0 = INACTIVE
1 = XCL
2 = PLB v4.6
3 = SDMA
4 = NPI
5 = PPC440MC
6 = VFBC
7 = MCB (Bidirectional)
8 = MCB (Unidirectional, Read Only)
9 = MCB (Unidirectional, Write Only)
Specific Port Interface Type.
MPMC GUI sets the value automatically and
places the correct parameter in the MHS file.
This value is an automatically calculated
parameter that can be overwritten; if set by the
user, it is not auto-calculated.
Specific Port Interface Type.
MPMC GUI sets the value automatically and
places the correct parameter in the MHS file.
This value is an automatically calculated
parameter that can be overwritten; if set by the
user, it is not auto-calculated.
PIM Base Address.
PIM High Address. MPMC supports a maximum
of 2 gigabytes of memory.
PIM Offset Address.
Read Data Path FIFO type.
Write Data Path FIFO type.
AddrAck Pipeline enable.
Read FIFO Port Side pipeline.
Read FIFO Memory Side pipeline.
Write FIFO Port Side pipeline.
Write FIFO Memory Side pipeline.
Enable Performance Monitor.
DS643 February 22, 2013
www.xilinx.com
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Product Specification