DS643 Datasheet, PDF (128/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
DMA Operation Descriptors
SDMA operation requires a common memory-resident data structure that holds the list of DMA operations to be
performed. This list of instructions is organized into what is referred to as a Descriptor Chain. The descriptor shown
in the following table is the basis for organizing the DMA operations as a Linked List. Descriptors are fetched
through the NPI. A similar mechanism is used for performing descriptor updates. Table 68 lists the SDMA
descriptors.
Table 68: SDMA Descriptors
Name
Description
NXTDESC_PTR
Next Descriptor Pointer
CURBUF_ADDR
Buffer Address
CURBUF_LENGTH
Buffer Length
STS_CTRL_APP0
APP1
APP2
APP3
APP4
Status/Control and
Application Data 0
Application Data 1
Application Data 2
Application Data 3
Application Data 4
Purpose
Specifies where in memory the next descriptor is to be fetched.
Specifies where in memory the buffer is for receiving or transmitting data.
For Transmit, specifies the amount of data in bytes that are to be transmitted.
For Receive, indicates the amount of space in bytes that is available to receive
data.
Status/Control for controlling and providing status to the DMA transfer of
application specific data.
Application specific data.
Application specific data.
Application specific data
Application specific data.
Table 69 shows the STS_CTRL_APP0 register bits.
Table 69: STS_CTRL_APP0
Bit(s)
Name
Type
Description
0
Error
Status
Set by the DMA when a error is encountered.
1
IrqOnEnd
Control
When set, causes the DMA to generate an interrupt event when the current descriptor
has been completed.
2
Reserved
N/A
Undefined
3
Completed
Status
When set, indicates that the current descriptor has been completed.
Transmit Channel (Control): Set by software in the descriptor indicating this buffer
4
SOP
Status/Control
descriptor is the first descriptor of a packet.
Receive Channel: (Status) Set by DMA in the descriptor indicating that a start of packet
was received on LocalLink.
Transmit Channel (Control): Set by software in the descriptor indicating this buffer
5
EOP
Status/Control
descriptor is the last descriptor of a packet.
Receive Channel (Status): Set by DMA in the descriptor indicating that an end of
packet was received on LocalLink.
6
Reserved
N/A
Undefined.
7
Reserved
N/A
Undefined.
8:31 Application Data 0
N/A
Application specific data.
Each field of the descriptor is 4 bytes in length and corresponds to either one of the DMA channel registers or user
application fields.
• For transmit channels, the application data fields (App0 to App4) of the first descriptor are transmitted as part
of the Header of the LocalLink Transmit Data stream.
• For receive channels, the Application Data Fields of the last buffer descriptor is updated with a portion of the
Footer of the LocalLink Receive Data stream.
See SDMA LocalLink Headers and Footers, page 136 for more information on LocalLink headers and footers.
DS643 February 22, 2013
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Product Specification