DS643 Datasheet, PDF (191/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
Additionally, some PIMs have optional pipeline stages that can be disabled:
XCL
PARAMETER C_XCL<Port_Num>_PIPE_STAGES = 0
PARAMETER C_XCL<Port_Num>_B_PIPE_STAGES = 0
MIB/PPC440MC
PARAMETER C_PPC440MC<Port_Num>_PIPE_STAGES = 0
• Choosing memory with a lower CAS latency at the target operating clock frequency reduces latency.
• Experiment with CUSTOM arbitration. By changing the arbitration priorities to favor critical ports, higher
throughput and potentially lower latency can be achieved for the critical ports. This is especially the case in a
heavily loaded system with many active ports.
• Use custom logic connected to an NPI interface rather than the using the PLB interface. The raw NPI interface
offers better direct performance to the memory controller. However, attaching custom logic to the NPI
interface might require more design and verification effort. When using NPI, larger bursts sizes offer higher
throughput and memory utilization than smaller burst sizes.
• In designs where the PowerPC 405 processor IPLB1 and DPLB1 ports are connected point-to-point to two
separate MPMC ports, these two PLB ports could be run 1:1 clock ratio to the memory clock.
By running 1:1 instead of 1:2 clock ratio, the throughput and latency can be improved by the higher interface
clock rate.
The MPMC PLB PIM instantiates specially optimized logic automatically when it is directly connected
point-to-point to a PowerPC 405 processor IPLB1 or DPLB1 port. This optimized logic can operate at a higher
clock frequency than a normal PLB bus-based connection.
• In Virtex-5 FXT FPGA designs using the PPC440MC interface, the ppc440mc_ddr2 IP core should be used
instead of MPMC whenever possible. The ppc440mc_ddr2 IP core is optimized as a single port DDR2
memory for the PowerPC 440 processor memory interface. The ppc440mc_ddr2 IP core offers row/bank
management, lower latency, and higher Fmax than MPMC. MPMC should only be used when SDRAM/DDR
memory support or multiple memory ports are needed. The performance advantage of ppc440mc_ddr2 is
especially high with 64-bit DDR2 memories. In this case ppc440mc_ddr2 offers a native 128-bit datapath
connection to the PowerPC440 block whereas the MPMC with PPC440MC PIM offers a maximum 64-bit
datapath to the PowerPC440 block.
• In Virtex-5 FX FPGA designs using the PPC440MC interface with the MPMC, the performance of DMA or burst
based transactions is better with a larger burst length setting (Parameter
C_PPC440MC<Port_Num>_BURST_LENGTH).
• The MPMC PLB v4.6 PIM translates non-cache burst transfers into NPI transactions of 16 word bursts
(C_SPLB<Port_Num>_NATIVE_DWIDTH = 32) or 32 word bursts (C_SPLB<Port_Num>_NATIVE_DWIDTH =
64). Non-cache PLB burst performance is maximized when the start address and burst length are aligned to
the corresponding NPI transactions. Shorter length PLB burst transfers or transfers that cross NPI transaction
boundaries could result in extra memory cycles where data is masked off or discarded. For example, if a DMA
engine is connected to the PLB port of MPMC, allocating the memory space of the DMA engine in the software
application to align to NPI transaction boundaries enables more efficient data transfers and improves system
performance.
MPMC Size Optimization
The following list identifies possible ways to reduce MPMC size:
• Reducing the number of ports has the biggest effect on reducing core size. For example instead of two separate
PLB ports to connect two PLB masters to MPMC, the two PLB masters can be connected to a PLB bus arbiter
and attached to a single MPMC port. This likely reduces system size, but might affect performance.
• Reducing down to a single port MPMC further decreases size because datapath switching logic can be
removed and the arbitration logic can be fully removed for added logic savings. Therefore the MPMC size
reduction is greater from two ports to one port than from three ports to two ports.
DS643 February 22, 2013
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Product Specification