DS643 Datasheet, PDF (184/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
32-Bit NPI Timing Diagrams
The following 32-bit NPI timing diagrams are illustrated:
• Word Write
• Word Read
• 8-Word, Cacheline Write
• 8-Word, Cacheline Read
Word Write
Figure 53 shows the following:
• A 32-bit NPI.
• A word Write transfer.
• The address is acknowledged in the same cycle as it is requested.
• The address is on a word boundary.
• The RdModWr must be asserted because the value of C_MEM_DATA_WIDTH is unknown.
• The Write Transfer Special Case is used (WrFIFO_Push is asserted after AddrAck).
X-Ref Target - Figure 53
MPMC_CLK0
AddrReq
AddrAck
Addr[31:0]
0x4
RNW
Size[3:0]
0x0
RdModWr
InitDone
WrFIFO_Empty
WrFIFO_AlmostFull
WrFIFO_Push
WrFIFO_Flush
WrFIFO_Data[31:0]
D0
WrFIFO_BE[3:0]
0xF
Figure 53: 32-Bit NPI Word Write
DS643_46_072407
DS643 February 22, 2013
www.xilinx.com
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Product Specification