DS643 Datasheet, PDF (4/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
Table 2: System Parameters (Cont’d)
Parameter Name
Default
Value
C_FAMILY
virtex5
C_IDELAYCTRL_LOC⁽⁴⁾
C_IODELAY_GRP⁽⁹⁾
C_MAX_REQ_ALLOWED
C_MCB_LOC⁽⁸⁾
NOT_SET
NOT_SET
1
NOT_SET
C_MCB_USE_EXTERNAL_BUFPLL⁽⁸⁾
0
C_MCB_RZQ_LOC⁽⁸⁾
NOT_SET
C_MCB_ZIO_LOC⁽⁸⁾
NOT_SET
C_MEM_ADDR_ORDER⁽⁸⁾
C_MEM_CALIBRATION_SOFT_IP⁽⁸⁾
C_MPMC_BASEADDR⁽¹⁾
C_MPMC_HIGHADDR⁽¹⁾
BANK_ROW_
COLUMN
FALSE
0xFFFFFFFF
0x00000000
C_MPMC_CLK_MEM_2X_PERIOD_PS⁽⁸⁾
1
C_MPMC_CTRL_BASEADDR⁽⁶⁾
C_MPMC_CTRL_HIGHADDR⁽⁶⁾
C_MPMC_CTRL_AWIDTH⁽⁶⁾
C_MPMC_CTRL_DWIDTH⁽⁶⁾
C_MPMC_CTRL_NATIVE_DWIDTH⁽⁶⁾
C_MPMC_CTRL_PLB_NUM_MASTERS⁽⁶⁾
C_MPMC_CTRL_PLB_MID_WIDTH⁽⁶⁾
0xFFFFFFFF
0x00000000
32
64
32
1
1
Allowable
Values
Description
STRING
virtex4, qvirtex4, qrvirtex4, virtex5, virtex6,
spartan3, aspartan3, spartan3a, spartan3adsp,
spartan3e, aspartan3e, aspartan3a, spartan6
STRING
IDELAYCTRL constraint locations (Hyphen
separated).
STRING
User-defined name used to group IDELAYCTRL
and IODELAY elements together.
1
Number of requests the MPMC can queue per port.
NOT SET,
Location of MCB for devices with multiple MCB
MEMC1, MEMC2, sites. See Spartan-6 FPGA C_MCB_LOC
MEMC3, MEMC4 Parameter, page 119 for more information.
Use an external BUFPLL_MCB to drive the MCB
clock. This option is used typically when two active
MCBs are on the same side of the FPGA and must
share a common BUFPLL_MCB. The second MCB
0,1
must then share the BUFPLL_MCB from the primary
MCB.
0 = Instantiate a BUFPLL_MCB inside MPMC
1 = Do not Instantiate a BUFPLL_MCB inside
MPMC.
NOT_SET
<Valid Pin
Locations>
Specifies the LOC constraint for the RZQ pin. This
parameter is translated to a core level LOC
constraint for the RZQ pin, and is required only if the
RZQ signal is connected. The valid values for the
parameter vary based on the MCB bank selected
with the C_MCB_LOC constraint. It must match the
pinout of the FPGA to the board.
NOT_SET
<Valid Pin
Locations>
Specifies the LOC constraint for the ZIO pin. This
parameter is translated into a core level LOC
constraint for the ZIO pin, and is required only if the
ZIO signal is connected. The valid values for the
parameter vary based on the MCB bank selected
with the C_MCB_LOC constraint. It must match the
pinout of the FPGA to the board.
BANK_ROW_
COLUMN,
ROW_BANK_
COLUMN
Defines the order with which the address bus is
divided into row, bank, and column bits
TRUE, FALSE
FALSE = Disable Soft Calibration Logic
TRUE = Enable Soft Calibration Logic (Strongly
recommended for Production silicon)
Valid Address MPMC PIMs shared base address.
Valid Address
MPMC PIMs shared high address. MPMC supports
a maximum of two gigabytes of memory.
1250-12500
Clock memory value is calculated automatically
based on what is connected to Port
MPMC_Clk_Mem_2x in XPS (for example a
clock_generator output or a signal/port with MHS
tag CLK_FREQ = xxxx.) The value can be
overwritten; if set by the user, it is not calculated.
Valid Address
MPMC CTRL PLB v4.6 base address. Must be 64K
aligned.
Valid Address MPMC CTRL PLB v4.6 high address.
32
PLB v4.6 Address width.
32, 64,128
PLB v4.6 Data width.
32
PLB v4.6 Native data width.
0-16
PLB v4.6 Number of masters on the bus.
0-4
PLB v4.6 Master ID width.
DS643 February 22, 2013
www.xilinx.com
4
Product Specification