DS643 Datasheet, PDF (40/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
Status Register Summary
The MPMC Status register is available only when one of set of registers is enabled. It consists of a single Read-only
register that displays static information about the MPMC that is useful for software to read to obtain hardware
configuration information. Table 35 through Table 37 provide the MPMC status register and bit definitions.
Table 34: MPMC Status Register Description
MPMC_CTRL Base Address
+ Offset (hex)
Register Name
Access
Type
Default Value
(hex)
Description
C_MPMC_CTRL_BASEADDR + 0x3000 MCSR0
RO
N/A
MPMC Ctrl Status Register 0
Table 35: MCSR0 Bit Definitions
Bit(s)
Field Name
Core
Access
Default
Value
Description
0
ECC CTRL Interface
Present
1 = MPMC has been synthesized with C_INCLUDE_ECC_SUPPORT =
1 and the error correcting code registers are present.
R
x
0 = MPMC has been synthesized with C_INCLUDE_ECC_SUPPORT =
0 and the error correcting code registers are not present.
1
Static PHY CTRL Interface
Present
R
2
Debug Registers CTRL
Interface Present
R
1 = MPMC has been synthesized with C_USE_STATIC_PHY = 1 and
the Static PHY registers are present.
x
0 = MPMC has been synthesized with C_USE_STATIC_PHY = 0 and
the Static PHY registers are not present.
1 = MPMC has been synthesized with C_DEBUG_ENABLE = 1 and the
Debug registers are present.
x
0 = MPMC has been synthesized with C_DEBUG_ENABLE = 0 and the
Debug registers are not present.
3
MPMC_CTRL Status
Interface Present
4:6
Reserved
7
PM CTRL Interface
Present
8:15 Reserved
16:19 Memory Type
1 = MPMC has been synthesized with C_INCLUDE_ECC_SUPPORT =
1 and/or C_USE_STATIC_PHY = 1 and/or C_DEBUG_ENABLE = 1
R
1
and/or C_PM_ENABLE = 1
0 = MPMC has not been synthesized with the MPMC_CTRL interface
(not possible)
R
x
Reserved
1 = MPMC has been synthesized with C_PM_ENABLE = 1 and the
Performance Monitor registers are present.
R
x
0 = MPMC has been synthesized with C_PM_ENABLE = 0 and the
Performance Monitor registers are not present.
R
x
Reserved
External Memory Type:
R
x
0x0 = SDRAM
0x1 = DDR
0x2 = DDR2
DS643 February 22, 2013
www.xilinx.com
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Product Specification