DS643 Datasheet, PDF (201/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
Latency Calculation Examples
For Tx:
Ignoring timing for buffer descriptor fetches (like in large block transfers), the throughput for Tx averages are = 32
words / (11 + Y + 36) LocalLink cycles.
Examples:
• If the application is for 16-bit DDR2 at 133 MHz, then Y = 25.
• If the LocalLink clock is 125 MHz, the throughput is 128 bytes / (11 + 25 + 36) * 8 ns = 222 MB/s
For Rx:
Ignoring timing for buffer descriptor fetches, the throughput for Rx average is = 32 words / (37 + 1 + 5) LocalLink
cycles. For example, if the LocalLink clock is 125 MHz, the throughput is: 128 bytes / (43) * 8 ns = 372 MB/s
Note: Assuming no throttling on NPI side and no throttling from LocalLink yields a high Rx Data throughput.
Latency Characteristics Assumptions
• Data re-alignment might be required
• No throttling on either NPI or LocalLink side
• No memory refresh
These latency timings are associated with a 1:1 clock ratio with Read Data Delay = 0. However, the timings for other
values of clock ratio and Read Data Delay are relatively the same because the LocalLink data throughput is the
system bottleneck.
XCL PIM Latency and Throughput
Table 98 describes the latency and throughput for the XCL PIM port. The table provides performance information
for common MPMC and XCL PIM configurations. The XCL PIM latency is measured from the first push of data into
the access FIFO until the first data is available on the read data FIFO. The throughput transactions were measured
by transferring 1 kilobyte of data in simulation.
The time between the first transaction and the last data item is used to divide the number of bytes transferred to
calculate the read throughput. The time measured between the first transaction and the last transaction has been
sent over the access FIFO is used for the write throughput calculation.
Table 98: XCL PIM Latency and Throughput
Pipeline
Settings
Memory Interface
Line Size
Port
Subtype
Memory to
XCL Clock
Ratio
Initial Transaction
Latency
(XCL Clocks)
Maximum Total
Data
Throughput of
XCL Port
(MB/s)
Spartan-3 FPGA Generation Reads
Default
DDR2 @ 133 MHz 32 bits
16
XCL
2:1
16
214
Default
DDR2 @ 133 MHz 16 bits
16
XCL
2:1
16
213
Default
DDR @ 83 MHz 16 bits
8
XCL
1:1
28
188
Default
DDR @ 83 MHz 16 bits
4
DXCL
1:1
28
127
None
DDR @ 83 MHz 16 bits
4
DXCL
1:1
22
157
Spartan-3 FPGA Generation Writes
Default
DDR2 @ 133 MHz 32 bits
16
XCL
2:1
N/A
225
Default
DDR2 @ 133 MHz 16 bits
16
XCL
2:1
N/A
225
Default
DDR @ 83 MHz 16 bits
8
XCL
1:1
N/A
165
DS643 February 22, 2013
www.xilinx.com
201
Product Specification