DS643 Datasheet, PDF (55/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
Address Path
The address path allows each PIM to have independent access. Each PIM supports 32-bit addresses. This allows at
least one 32-bit address from each PIM to be acknowledged simultaneously. The control path then determines the
order in which the addresses go to memory. See MPMC Optimization, page 190 for more details.
Base/High/Offset Parameters
Each PIM has PIM-specific Base/High/Offset address parameters. See Personality Interface Modules, page 121 for
information on the correct address for the PIM you are using. The MPMC parameters are listed in Design
Parameters, page 3.
Address Encoding
The MPMC does not perform address range validation, and MPMC responds to all addresses, so it is the
responsibility of the PIM to ensure that valid addresses are passed across the NPI interface. The address path is
responsible for translating the address into an encoded address that adheres to SDRAM, DDR, or DDR2 memory
specifications.
The following memory parameters are used to encode the address:
• C_MEM_DATA_WIDTH
• C_MEM_PART_NUM_COL_BITS
• C_MEM_PART_NUM_ROW_BITS
• C_MEM_PART_NUM_BANK_BITS
• C_MEM_NUM_RANKS
• C_MEM_NUM_DIMMS
The memory address offsets are as follows:
• col_addr_startbit = log2(C_MEM_DATA_WIDTH/8)
• row_addr_startbit = col_addr_startbit + C_MEM_PART_NUM_COL_BITS
• bank_addr_startbit = row_addr_startbit + C_MEM_PART_NUM_ROW_BITS
• rank_addr_startbit = bank_addr_startbit + C_MEM_PART_NUM_BANK_BITS
• dimm_addr_startbit = rank_addr_startbit + C_MEM_NUM_RANKS
• total_addr_startbit = dimm_addr_startbit + C_MEM_NUM_DIMMS
Table 38 shows the address column, row, bank, rank, DIMM, and total memory address.
Table 38: Address Type and Corresponding Signal
Memory Address Type
Corresponds to:
Column
PIM<Port_Num>_Addr[row_addr_startbit: col_addr_startbit]
Row
Bank
PIM<Port_Num>_Addr[bank_addr_startbit-1:row_addr_startbit]
PIM<Port_Num>_Addr[rank_addr_startbit-1:bank_addr_startbit]
Rank
DIMM
PIM<Port_Num>_Addr[dimm_addr_startbit-1:rank_addr_startbit]
PIM<Port_Num>_Addr[total_addr_startbit-1:dimm_addr_startbit]
Total memory space
PIM<Port_Num>_Addr[total_addr_startbit-1:0]
You can set the base and high addresses of your custom PIM to cover this address space. Standard PIMs (such as
PLB and XCL PIMs) have address range and offset parameters to handle how addresses are mapped from the bus
interface to the physical memory.
DS643 February 22, 2013
www.xilinx.com
55
Product Specification