DS643 Datasheet, PDF (146/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
SDMA Descriptor Update
Figure 28 shows the MPMC port interface timing for a descriptor update. The SDMA uses 8-word cacheline writes
to perform a descriptor update. The SDMA push the data into the MPMC Write FIFO if there is space available.
After the data has been pushed to the FIFO, the SDMA makes a Write request to the MPMC.
X-Ref Target - Figure 28
0ns
20ns
PI_Clk 2 4 6 8
PI_Addr[31:0]
PI_AddrReq
PI_RNW
PI_AddrAck
PI_Size[3:0]
PI_RdFIFO_Data[63:0]
PI_RdFIFO_Pop
PI_RdFIFO_RdWdAddr[3:0]
PI_RdFIFO_DataAvailable
PI_RdFIFO_Empty
PI_RdFIFO_Flush
PI_WrFIFO_Data[63:0]
D0
PI_WrFIFO_BE[7:0]
FF
PI_WrFIFO_Push
PI_WrFIFO_AlmostFull
PI_WrFIFO_Flush
40ns
D1
FF
60ns
80ns
A0
2
D2
D3
FF
FF
Figure 28: Descriptor Update Timing
100ns
DS643_29_071307
SDMA Transmit Data Read
Figure 29 shows a transmit data read (fetch) from the MPMC. The SDMA uses 32-word (or 16-doubleword) Reads
to fetch data for transmitting across LocalLink. Reads always begin at 32-word boundaries. The SDMA uses the
data starting with the current buffer address only and ignores additional invalid data fetched due to the 32-word
boundary restriction.
X-Ref Target - Figure 29
0ns
PI_Clk
PI_Addr[31:0] ^A0
PI_AddrReq
PI_RNW
PI_AddrAck
PI_Size[3:0] ⁴
PI_RdFIFO_Data[63:0]
PI_RdFIFO_Pop
PI_RdFIFO_RdWdAddr[3:0]
PI_RdFIFO_Empty
PI_RdFIFO_Flush
50ns
100ns
150ns 200ns
250ns
300ns
Time from PI_Addr Req to Read Data Available will vary
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
0
350ns
PI_WrFIFO_Data[63:0]
PI_WrFIFO_BE[7:0]
PI_WrFIFO_Push
PI_WrFIFO_AlmostFull
PI_WrFIFO_Flush
Figure 29: Transmit Data Read
DS643_30_071307
DS643 February 22, 2013
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146
Product Specification