DS643 Datasheet, PDF (93/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
• In the integrated MIG flow, the constraints and some parameters are handled automatically. The MIG
constraints pass into a core-level constraint file that is merged into the ISE® tools during ngdbuild. The
core-level constraint file contains the memory interface pin location, timing, and area constraints needed for
the design.
- The EDK system.ucf should not contain any memory interface pinout, timing, or placement constraints
as they are handled in the integrated flow using the core-level UCF files.
- The C_MMCM_EXT_LOC, C_MEM_NDQS_COLx, and C_MEM_DQS_LOC_COLx parameters are set automatically
for Virtex-6 FPGAs. If you are not using the Clock Generator core v3.02.a or greater you must ensure the
external MMCM driving the MPMC clocks is set correctly.
• Consider verifying that the design correctly runs through all back end tools, is correctly placed and routed,
meets timing, and shows no errors or significant warnings before committing the generated pinout to board
layout.
- Verify in the PAR report that all memory interface pins are “LOCed”. Check the.pad file to view or debug
the final memory interface pin locations and I/O standards.
- Review the information in this document and the Memory Interface Solutions User Guide to ensure key
aspects of the MIG PHY such as the template router (Spartan-3 FPGAs) or DIRT strings (Virtex-5 FPGAs)
have been placed and routed correctly.
• When the integrated MIG flow is enabled (C_USE_MIG_FLOW = 1), MPMC scripts are invoked during the
Platgen EDK build phase that check for changes to MPMC configurations that would require MIG to be rerun.
If the script flags an MPMC change such as a new memory width, the script generates an error requesting that
user rerun the MIG GUI.
• Perform a hardware clean in XPS before rebuilding a design where the MIG GUI settings have been changed.
Standalone MIG GUI Flow
The Standalone MIG GUI flow offers the highest degree of flexibility because the full capability of the MIG GUI is
made available. This standalone flow also provides greater visibility into the intermediate files and to the steps for
generating an MPMC UCF from the output of the MIG GUI.
This option is also useful if you use a standalone MIG-based memory controller on the same hardware board
platform. This Standalone MIG GUI is the flow used in previous versions of the MPMC. The following steps
describe how to use the Standalone MIG GUI option:
1. Ensure that you have downloaded any available CORE Generator tool technology IP updates.
2. Create a CORE Generator tool project with the same FPGA and package to match the EDK project settings. The
MIG tool is available under the View By Function tab > Memories and Storage Elements > Memory
Interface Generators.
3. Ensure that the MIG tool is set to Verilog output mode:
(Project > Project Options > Generation Tab > Design Entry > Verilog.)
4. Run the MIG tool version from the CORE Generator tool, set up memory part information, data widths, I/O
banking locations, and so forth. (If necessary, click the User Guide button and review the board layout
requirements for the memory interface.)
5. Click the Generate button to generate a MIG pinout.
6. Clicking the Generate button also produces a MIG hardware test bench design at:
<coregen_project>/example_design. This test bench design can be run as a standalone hardware
design on the board to help test/debug the memory PHY interface.
7. After running the MIG tool, take the UCF created by MIG located at:
<coregen_project>/<user_design>/par/<coregen_project>.ucf.
DS643 February 22, 2013
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Product Specification