DS643 Datasheet, PDF (200/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
Table 97: SDMA Latency Expectations (Cont’d)
Operation
Tx
Tx
Tx
Tx
Tx
Tx
Tx
Tx
Tx
Rx
Rx
Rx
Rx
Rx
Latency Between
LocalLink
Clock Cycles
Notes
Address Acknowledge from NPI port.
Data Available on NPI.
Y
Memory-dependent latency. See Table 95,
page 194 for standard values.
Data available on NPI
first 32-word Block Transmit complete on
LocalLink.
33
Assumes complete 32-word transfer (with no flush
to NPI⁽¹⁾)
First 32-word block Transmit complete NPI.
Address Request for second (or any subsequent,
except last) 32-word block burst for transmission
14
16 for Read FIFO Port Side Pipeline = 1.
on LocalLink.
Address Acknowledge from NPI port.
Data Available on NPI.
Y
Memory-dependent latency. See Table 95,
page 194 for standard values.
Data available on NPI.
Second 32-word block Transmit complete on
LocalLink.
34
Assumes complete 32-word transfer (with no flush
to NPI⁽¹⁾)
Second to Last 32-word Block Transmit complete
on LocalLink.
NPI Address Request for last 32-word block burst
14
16 for Read FIFO Port Side Pipeline = 1.
for transmission on LocalLink.
NPI Address Request.
Data available on NPI.
Y
Memory-dependent latency. See Table 95,
page 194 for values.
Data available on NPI.
Last 32-word block Transmit complete on
LocalLink.
34
Assumes complete 32-word transfer (with no flush
to NPI⁽¹⁾)
Last 32-word Block Transmit complete on
LocalLink.
14
TX buffer descriptor Write update complete.
First Rx Source Ready (on LocalLink side).
Address Request for first 32-word block Write on
NPI.
10
Assuming Rx Destination is ready to receive the
data
First push issued on NPI for a burst Write.
NPI Addrreq issued on NPI for burst Write.
32
Address Request for any 32-word block Write on
NPI Address.
Acknowledge from NPI.
1
Assuming usual response time from the MPMC
RxSrcRdy asserted for second (or any
subsequent) 32-word block.
First push issued on NPI side.
5
Assuming Rx Destination is ready to receive the
data
Last 32-word Block write complete on NPI,
Rx buffer descriptor Write update complete.
12
Notes:
1. If less than 32 words are required, a flush is issued to NPI and the number of clock cycles required to complete the transmit operation = 5
+ number of words to be transmitted.
DS643 February 22, 2013
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Product Specification