DS643 Datasheet, PDF (166/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
VFBC Read Data Interface
The Read data interface is an asynchronous FIFO with a configurable depth, data width, and almost empty flag. The
data width can be configured as 8, 16, 32, or 64 bits.
Data is popped off of the FIFO during the same clock cycle as when the VFBC<Port_Num>_Rd_Read signal is active.
The VFBC<Port_Num>_Rd_Flush signal flushes the data that is in the FIFO but keeps the current read command
active in the command FIFO. Asserting the FIFO Flush returns the internal read/write FIFO pointers to zero. The
VFBC<Port_Num>_Rd_Reset signal is used to flush the data in the FIFO and also flush the read command from the
command FIFO. The VFBC<Port_Num>_Rd_End_Burst signal is used only when the transfer is not a multiple of the
burst size. If the transfer ends on a boundary that is not 32-word aligned, this signal must be asserted High during
the last word transferred.
Figure 41 shows a typical Read operation. Notes on the operation are listed after the figure.
X-Ref Target - Figure 41
VFBC<Port_NUM>_Cmd_Clk/Rd_Clk
VFBC<Port_NUM>_Cmd_Reset/Rd_Reset
VFBC<Port_NUM>_Cmd_Write
VFBC<Port_NUM>_Cmd_Data[31:0]
VFBC<Port_NUM>_Cmd_Full (Out)
VFBC<Port_NUM>_Rd_Read
VFBC<Port_NUM>_Rd_Data (Out)
VFBC<Port_NUM>_Rd_End_Burst
C0 C1 C2 C3
C0 C1 C2 C3
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
VFBC<Port_NUM>_Rd_Almost_Empty (Out)
VFBC<Port_NUM>_Rd_Empty (Out)
X10913
Figure 41: VFBC Read Timing
Notes:
• Bit 31 in Command Word C1 must be set to zero for this to be a Read operation.
• The Command Words C0, C1, C2, and C3 must be Written before the data can be Read from the data FIFO.
• The Command Words can be written during a Read operation for the next Read operation.
• Figure 41 shows one cycle between VFBC<Port_Num>_Rd_End_Burst and the next burst; although, zero to
any number of cycles can exist between Read transactions.
• If the VFBC<Port_Num>_Rd_End_Burst signal is used, it must be asserted during the same cycle as the last
valid data Read and can be on D0-D7 cycles.
• The VFBC<Port_Num>_Rd_End_Burst signal is optional in this diagram and could be always set Low.
VFBC<Port_Num>_Rd_End_Burst needs to be used only if the transfer does not end on a 32-word boundary.
• The VFBC can accept a data transfer on every clock cycle given that VFBC Read FIFO is not Empty and that the
MPMC memory interface throughput can accommodate the data rate of the VFBC client.
VFBC Transfer Examples
This section provides examples of typical video applications, the VFBC setup used to accomplish these
applications, and the resultant transfers.
Frame Mode 1080p to VGA Window
Figure 42 is an example of a 1080p @ 60fps video source being written to a frame store in external memory. A VGA@
60fps display is reading a 640x480 window of the 1920x1080 source video from the frame store.
DS643 February 22, 2013
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Product Specification