DS643 Datasheet, PDF (18/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
DDR, DDR2, and DDR3 I/O Signals
DDR I/O Signals (Spartan-3, Virtex-4, and Virtex-5 FPGAs Only)
Table 13: DDR I/O Signals
Signal Name⁽¹⁾
Direction
Init Status
Description
DDR_Addr
DDR_BankAddr
DDR_CAS_n
DDR_CE
DDR_CS_n
DDR_Clk
DDR_Clk_n
DDR_DM
DDR_DQ⁽³⁾
DDR_DQS⁽³⁾
DDR_DQS_DIV_O⁽²⁾
DDR_DQS_DIV_I⁽²⁾
DDR_RAS_n
DDR_WE_n
Output
Output
Output
Output
Output
Output
Output
Output
In/Out
In/Out
Output
Input
Output
Output
x
Row/Column address.
x
Bank address.
1
Command input.
0
1 = Clock enabled. (memory CKE signal)
1
0 = Chip select enabled.
0
Clock to memory.
1
Inverted clock to memory.
x
Data mask outputs.
x
Data.
x
Data strobe.
x
Timing loop signal.
x
Timing loop signal.
1
Command input.
1
Command input.
Notes:
1. For detailed signal descriptions, see device-specific data sheets.
2. Required when using MIG-based Spartan-3/3A/3AN/3A DSP/3E FPGA PHY.
3. The MHS signal connecting this port and the MHS external port must have the same name. See
www.xilinx.com/support/answers/14264.htm. Reference Documents, page 215 has a link to this topic.
DDR2 I/O Signals (Spartan-3, Virtex-4, Virtex-5, and Virtex-6 FPGAs Only)
Table 14: DDR2 I/O Signals
Signal Name⁽¹⁾
Direction Init Status
Description
DDR2_Addr
DDR2_BankAddr
DDR2_CAS_n
DDR2_CE
DDR2_CS_n
DDR2_Clk
DDR2_Clk_n
Output
Output
Output
Output
Output
Output
Output
x
Row/Column address.
x
Bank address.
1
Command input.
0
1 = Clock enabled.
1
0 = Chip select enabled.
0
Clock to memory.
1
Inverted clock to memory.
DDR2_DM
DDR2_DQ⁽³⁾
DDR2_DQS⁽³⁾
DDR2_DQS_DIV_I⁽²⁾
DDR2_DQS_DIV_O⁽²⁾
DDR2_DQS_n⁽⁴⁾
Output
In/Out
In/Out
Input
Output
In/Out
x
Data mask outputs.
x
Data.
x
Data Strobe.
x
Timing loop signal.
x
Timing loop signal.
x
Inverted Data Strobe.
DDR2_ODT
DDR2_RAS_n
Output
Output
On-Die-Termination signal. Care must be taken when connecting
0
these pins to your memory when you have more than one rank;
there is a direct relationship to the DDR2_CS_n pins.
1
Command input.
DS643 February 22, 2013
www.xilinx.com
18
Product Specification