DS643 Datasheet, PDF (195/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
Table 95: NPI Latency and Throughput (Cont’d)
Number of
Ports
Pipeline
Settings
Memory Interface
NPI Width MPMC NPI
(Bits) Burst Type
8
Default
DDR3 @ 400 MHz 32 bits
64
64 Word Burst
1
Default
DDR3 @ 400 MHz 32 bits
32
64 Word Burst
2
Default
DDR3 @ 400 MHz 32 bits
32
64 Word Burst
1
All Pipelines Off DDR3 @ 400 MHz 32 bits
64
64 Word Burst
1-8
Default
DDR3 @ 400 MHz 16 bits
64
32 Word Burst
1-8
Default
DDR3 @ 400 MHz 16 bits
64
64 Word Burst
1-8
Default
DDR3 @ 400 MHz 32 bits
64
16 Word Burst
1-8
Default
DDR2 @ 333 MHz 32 bits
64
16 Word Burst
1
Default
DDR2 @ 333 MHz 32 bits
64
32 Word Burst
8
Default
DDR2 @ 333 MHz 32 bits
64
64 Word Burst
Spartan-6 FPGA Reads
1
N/A
DDR2/DDR3 @ 400 MHz
16 bits / NPI @ 100 MHz
32
16 Word Burst
4
N/A
DDR2/DDR3 @ 400 MHz
16 bits / NPI @ 100 MHz
32
16 Word Burst
1
N/A
DDR2/DDR3 @ 400 MHz
16 bits / NPI @ 100 MHz
32
32 Word Burst
4
N/A
DDR2/DDR3 @ 400 MHz
16 bits / NPI @ 100 MHz
32
32 Word Burst
1
N/A
DDR2/DDR3 @ 400 MHz
16 bits / NPI @ 100 MHz
32
64 Word Burst
4
N/A
DDR2/DDR3 @ 400 MHz
16 bits / NPI @ 100 MHz
32
64 Word Burst
1
N/A
DDR2/DDR3 @ 400 MHz
16 bits / NPI @ 100 MHz
64
16 Word Burst
2
N/A
DDR2/DDR3 @ 400 MHz
16 bits / NPI @ 100 MHz
64
16 Word Burst
1
N/A
DDR2/DDR3 @ 400 MHz
16 bits / NPI @ 100 MHz
64
32 Word Burst
2
N/A
DDR2/DDR3 @ 400 MHz
16 bits / NPI @ 100 MHz
64
32 Word Burst
1
N/A
DDR2/DDR3 @ 400 MHz
16 bits / NPI @ 100 MHz
64
64 Word Burst
2
N/A
DDR2/DDR3 @ 400 MHz
16 bits / NPI @ 100 MHz
64
64 Word Burst
Spartan-3 FPGA Generation Writes
1-8
Default
DDR@100 MHz 32 bits
64
16 Word Burst
1-8
Default
DDR@100 MHz 32 bits
64
32 Word Burst
1-8
Default
DDR@100 MHz 32 bits
64
64 Word Burst
1-8
Default
DDR2@133 MHz 16 bits
32
16 Word Burst
1-8
Default
DDR2@133 MHz 32 bits
64
16 Word Burst
1-8
Default
DDR2@133 MHz 32 bits
64
32 Word Burst
1-8
Default
DDR2@133 MHz 32 bits
64
64 Word Burst
1-8
Default
DDR@83 MHz 16 bits
32
16 Word Burst
1-8
All Pipelines Off DDR@83 MHz 16 bits
32
16 Word Burst
Initial
Transaction
Latency
(MPMC_Clk0)
30
30
30
27
30
30
30
29
29
29
11
11
11
11
11
11
10
10
10
10
10
10
N/A⁽¹⁾
N/A⁽¹⁾
N/A⁽¹⁾
N/A⁽¹⁾
N/A⁽¹⁾
N/A⁽¹⁾
N/A⁽¹⁾
N/A⁽¹⁾
N/A⁽¹⁾
Maximum Total
Data Throughput
(MB/s)
2003
775
1538
1502
1006
1226
968
803
1227
1672
237
809
295
1062
342
1261
441
813
565
1068
661
1265
400
533
640
328
474
656
813
222
222
DS643 February 22, 2013
www.xilinx.com
195
Product Specification