DS643 Datasheet, PDF (148/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
SDMA Receive LocalLink
An example receive LocalLink transfer of 8 words is shown in Figure 32.
Note: During a receive request the last buffer descriptor of a packet is populated with the APP fields of the LocalLink footer.
X-Ref Target - Figure 32
0ns
50ns
LLink_Clk 2 4 6 8
TX_D[31:0]
TX_REM[3:0]
TX_SOF
TX_SOP
TX_EOP
TX_EOF
TX_Src_Rdy
TX_Dst_Rdy
100ns
150ns
200ns
RX_D[31:0]
RX_REM[3:0]
RX_SOF
RX_SOP
RX_EOP
RX_EOF
RX_Src_Rdy
RX_Dst_Rdy
D0 D1 D2 D3 D4 D5 D6 D7 Ftr0 Ftr1 Ftr2 Ftr3 Ftr4 Ftr5 Ftr6 Ftr7
0
DS607_26_041707
Figure 32: Receive LocalLink Timing
SDMA Registers
The SDMA registers are detailed in the following subsections:
• Next Descriptor Pointer (TX_NXTDESC_PTR and RX_NXT_DESC_PTR) Offsets: 0x00 and 0x20
• Current Buffer Address (TX_CURBUF_ADDR and RX_CURBUF_ADDR) Offsets: 0x04 and 0x24
• Current Buffer Length (TX_CURBUF_LENGTH, RX_CURBUF_LENGTH) Offsets:0x08 and 0x28
• Current Descriptor Pointer (TX_CURDESC_PTR, RX_CURDESC_PTR) Offsets: 0x0C and 0x2C
• Tail Descriptor Pointer (TX_TAILDESC_PTR and RX_TAILDESC_PTR) Offsets: 0x10 and 0x30
• Channel Control Register (TX_CHNL_CTRL and RX_CHNL_CTRL) Offsets: 0x14 and 0x34
• Interrupt Status Register (TX_IRQ_REG and RX_IRQ_REG) Offsets: 0x18 and 0x38
• Channel Status Register (TX_CHNL_STS and RX_CHNL_STS) Offsets: 0x1C and 0x3C
• DMA Control Register Offset: 0x40
Next Descriptor Pointer (TX_NXTDESC_PTR and RX_NXT_DESC_PTR)
Offsets: 0x00 and 0x20
The Next Descriptor Pointers TX_NXTDESC_PTR (Transmit) and RX_NXT_DESC_PTR (Receive), are loaded from the
Next Descriptor Pointer field in the current descriptor for the respective channel. This value is kept in the respective
SDMA register until the SDMA has completed all DMA transactions within the DMA transfer. After DMA
transactions are complete, the current descriptor is complete and the SDMA_COMPLETED bit is set in the respective
status register. The current descriptor is written to update the status of the STS_CTRL_APP0 field within the
descriptor.
Then the SDMA evaluates if there is a halt condition that occurs when the Current Descriptor Pointer equals the Tail
Descriptor Pointer.
DS643 February 22, 2013
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148
Product Specification