DS643 Datasheet, PDF (49/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
Dual PowerPC 405 Processor Use Case
Figure 3 shows an example of two PowerPC 405 processors connected directly to an MPMC module.
X-Ref Target - Figure 3
BRAM
Device
IPLB1
PPC405
IPLB0
DPLB1
DPLB0
PLB
PIM
(IPLB)
PLB
PIM
(DPLB)
PLB
PIM
Device
PLB
ARB
BRAM
low bandwidth
Device
low bandwidth
Device
IPLB1
PPC405
IPLB0
DPLB1
DPLB0
high bandwidth
Config
Master
PLB Device PLB
Port
Port
PLB
PIM
(IPLB)
PLB
PIM
(DPLB)
PLB
PIM
MPMC
PLB
PIM
Memory
PLB
ARB
Figure 3: Dual Processor PowerPC Use Case
DS643_03_082007
On the first PowerPC 405 processor:
• The IPLB1 and DPLB1 ports of the first PowerPC 405 processor are connected to the first two MPMC PLB
PIMs. These are point to point connections for improved performance. Additionally, the PLB PIMs are
designated as IPLB and DPLB PIMs to allow for performance optimizations inside the PIM.
• The IPLB0 and DPLB0 ports of the first PowerPC 405 processor are connected to the PLB Bus attached to the
third PLB PIM. Also attached to the PLB Bus are block RAM memory, which can be used to boot code and
other PLB devices necessary to a particular application.
On the second PowerPC 405 processor:
• The IPLB1 and DPLB1 ports of the second PowerPC 405 processor are connected directly to the fourth and fifth
PLB PIMs.
• The IPLB0 and DPLB0 ports of the second PowerPC 405 processor are connected to the PLB bus attached to the
sixth PLB PIM. Also on this PLB bus are the block RAM memory, which can be used to boot code and other
“low-bandwidth” PLB devices.
• On the seventh PLB PIM is a “high bandwidth” PLB device. This device has a direct connection to MPMC to
improve performance. The configuration PLB port of this high bandwidth device is connected to the sixth PLB
PIM to allow configuration from the second PowerPC 405 processor.
DS643 February 22, 2013
www.xilinx.com
49
Product Specification