DS643 Datasheet, PDF (194/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
NPI PIM Latency and Throughput
The latency and throughput at the NPI level reflects the performance of the MPMC core because NPI is the native
interface of the MPMC. Table 95 provides the NPI estimations by port, pipeline setting, memory interface, NPI
width (in bits), and NPI burst type as well as the initial transaction latency, and maximum data throughput.
Table 95: NPI Latency and Throughput
Number of
Ports
Pipeline
Settings
Memory Interface
NPI Width MPMC NPI
(Bits) Burst Type
Spartan-3 FPGA Generation Reads
1-8
Default
DDR@100 MHz 32 bits
64
16 Word Burst
1-8
Default
DDR@100 MHz 32 bits
64
32 Word Burst
1-8
Default
DDR@100 MHz 32 bits
64
64 Word Burst
1-8
Default
DDR2@133 MHz 16 bits
32
16 Word Burst
1-8
Default
DDR2@133 MHz 32 bits
64
16 Word Burst
1-8
Default
DDR2@133 MHz 32 bits
64
32 Word Burst
1-8
Default
DDR2@133 MHz 32 bits
64
64 Word Burst
1-8
Default
DDR@83 MHz 16 bits
32
16 Word Burst
1-8
All Pipelines Off DDR@83 MHz 16 bits
32
16 Word Burst
Virtex-4/Virtex-5 FPGA Reads
1-8
Default
DDR2@200 MHz 32 bits
64
16 Word Burst
1-8
Default
DDR2@200 MHz 32 bits
64
32 Word Burst
1-8
Default
DDR2@200 MHz 32 bits
64
64 Word Burst
1
Default
DDR2@200 MHz 64 bits
64
16 Word Burst
2-8
Default
DDR2@200 MHz 64 bits
64
16 Word Burst
1-8
Default
DDR2@200 MHz 64 bits
64
32 Word Burst
2
Default
DDR2@200 MHz 64 bits
64
32 Word Burst
3-8
Default
DDR2@200 MHz 64 bits
64
32 Word Burst
1
Default
DDR2@200 MHz 64 bits
64
64 Word Burst
2
Default
DDR2@200 MHz 64 bits
64
64 Word Burst
3-8
Default
DDR2@200 MHz 64 bits
64
64 Word Burst
1-8
Default
DDR@100 MHz 32 bits
64
16 Word Burst
1-8
Default
DDR@100 MHz 32 bits
64
32 Word Burst
1-8
Default
DDR@100 MHz 32 bits
64
64 Word Burst
1-8
All Pipelines Off DDR@100 MHz 32 bits
64
16 Word Burst
1-8
All Pipelines Off DDR@100 MHz 32 bits
64
32 Word Burst
1-8
All Pipelines Off DDR@100 MHz 32 bits
64
64 Word Burst
Virtex-6 FPGA Reads
1-8
Default
DDR3 @ 400 MHz 32 bits
64
16 Word Burst
1
Default
DDR3 @ 400 MHz 32 bits
64
32 Word Burst
8
Default
DDR3 @ 400 MHz 32 bits
64
32 Word Burst
1
Default
DDR3 @ 400 MHz 32 bits
64
64 Word Burst
2
Default
DDR3 @ 400 MHz 32 bits
64
64 Word Burst
4
Default
DDR3 @ 400 MHz 32 bits
64
64 Word Burst
Initial
Transaction
Latency
(MPMC_Clk0)
24
24
24
25
25
25
25
24
20
23
23
23
23
23
23
23
23
23
23
23
20
20
20
16
16
16
30
30
30
30
30
30
Maximum Total
Data Throughput
(MB/s)
533
640
711
406
656
813
923
267
267
853
1113
1313
800
1067
1113
1600
1707
1313
1600
2226
533
640
711
533
640
711
968
1408
1477
1502
1802
1927
DS643 February 22, 2013
www.xilinx.com
194
Product Specification