DS643 Datasheet, PDF (89/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
Memory Interface Generator PHY Interface
The following subsections describe the Memory Interface Generator (MIG)-based PHY interface:
• MIG PHY Features
• MIG-Based PHY Design Considerations
• MIG/MPMC Tool Flow
• MIG Spartan-3 FPGA Design Considerations
• Board Considerations
• MIG Virtex-4 FPGA Design Considerations
• Additional MIG Information
MIG PHY Features
The MIG-based PHY interface contains:
• Input and output flip-flops
• Read data delay logic
• Data capture logic
• Memory initialization logic
The read data delay logic uses IDELAYs for Virtex-4, Virtex-5, and Virtex-6 families, and Look-Up Table (LUT)
delays for Spartan-3 devices. The delay logic is used to align the middle of the valid read data to the MPMC_Clk0
clock edge. This is necessary to accommodate for variations in trace delays on different boards. The delay elements
change the time that the read data arrives at the FPGA to align it to the main clock.
In the Virtex-4, Virtex-5, and Virtex-6 families, this alignment is done as part of the memory initialization logic. At
the end of the initialization or configuration sequence, the PHY issues dummy Write and Read commands.
The delay logic then determines the edges of the input data and shifts the input data to allow MPMC_Clk0 to capture
the data. To ensure a robust interface, match the trace lengths for the data signals to the corresponding data strobe
signal and ensure that the proper FPGA I/O pin selections are made as described in the Memory Interface Solutions
User Guide. Reference Documents, page 215 has a link to the MIG web page.
In DDR, DDR2, and DDR3 cases, the data capture logic takes the DDR read data and turns it into Single Data Rate
(SDR) data. The PHY then pushes the data into the datapath FIFOs, making it available to the NPI and then to any
additional user PIMs.
For more information on the use of IDELAY in DDR, DDR2 and DDR3 applications see the Memory Interfaces Data
Capture Using Direct Clocking Technique document. The Reference Documents, page 215 contains a link to this
document.
For more information about the MIG physical interface design, register and download the MIG design. The
Reference Documents, page 215 contains a link to the Xilinx Memory web page where the MIG design is located.
DS643 February 22, 2013
www.xilinx.com
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Product Specification