DS643 Datasheet, PDF (20/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
MCB PIM I/O Signals
Table 16: DDR, LPDDR, DDR2, and DDR3 MCB PIM I/O Signals (Spartan-6 FPGAs Only)
Signal Name
Direction
Init Status
Description
mcbx_dram_addr
mcbx_dram_ba
mcbx_dram_cas_n
mcbx_dram_cke
mcbx_dram_clk
mcbx_dram_clk_n
mcbx_dram_ddr3_rst
mcbx_dram_dq
mcbx_dram_dqs
mcbx_dram_dqs_n
mcbx_dram_ldm
mcbx_dram_odt
mcbx_dram_ras_n
mcbx_dram_udqs
mcbx_dram_udqs_n
mcbx_dram_udm
mcbx_dram_we_n
rzq
zio
Output
Output
Output
Output
Output
Output
Output
In/Out
In/Out
In/Out
Output
Output
Output
In/Out
In/Out
Output
Output
In/Out
In/Out
x
Row/Column address.
x
Bank address.
1
Command input.
0
1 = Clock enabled.
0
Clock to memory.
1
Inverted clock to memory.
0
Inverted DDR3 Reset. This is an active-Low signal to be
connected directly to the DDR3 component.
x
Data.
x
Data Strobe.
x
Inverted Data Strobe.
x
Lower Data Mask.
0
On-Die-Termination signal.
1
Command input.
x
Upper Data Strobe.
x
Upper Inverted Data Strobe.
x
Upper Data Mask.
1
Command input.
Used by soft calibration logic
x
(C_MEM_CALIBRATION_SOFT_IP = TRUE) to match
input impedance to external resistor.
Used by soft calibration logic
x
(C_MEM_CALIBRATION_SOFT_IP = TRUE) to match
input impedance to external resistor.
DS643 February 22, 2013
www.xilinx.com
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Product Specification