DS643 Datasheet, PDF (145/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
SDMA Transaction Timing
The following subsections describe transaction timing for the SDMA.
• SDMA Descriptor Fetch
• SDMA Descriptor Update
• SDMA Transmit Data Read
• SDMA Receive Data Write
• SDMA Transmit LocalLink
• SDMA Receive LocalLink
SDMA Descriptor Fetch
Figure 27 shows NPI port interface timing for a descriptor fetch. The SDMA uses 8-word, cacheline reads to
perform a descriptor fetch. The timing from when the SDMA makes a request of the NPI depends on arbitration in
the MPMC. The SDMA monitors PI_RdFIFO_Empty to determine when to begin to pop data out of the MPMC read
FIFO.
X-Ref Target - Figure 27
0ns
PI_Clk
PI_Addr[31:0]
PI_AddrReq
PI_RNW
PI_AddrAck
PI_Size[3:0]
PI_RdFIFO_Data[63:0]
PI_RdFIFO_Pop
PI_RdFIFO_RdWdAddr[3:0]
PI_RdFIFO_Empty
PI_RdFIFO_Flush
PI_WrFIFO_Data[63:0]
PI_WrFIFO_BE[7:0]
PI_WrFIFO_Push
PI_WrFIFO_AlmostFull
PI_WrFIFO_Flush
20ns
40ns
A0
60ns
80ns
100ns
120ns
2
Time from PI_Addr Req to Read Data Available will vary
D0
D1
D2
D3
0
2
4
6
Figure 27: Descriptor Fetch Timing
140ns
X11044
DS643 February 22, 2013
www.xilinx.com
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Product Specification