DS643 Datasheet, PDF (104/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
Static PHY Implementation
Figure 11 shows the Static PHY interface read logic. The RDDATA_SWAP_RISE stage is not present for SDRAM
designs.
X-Ref Target - Figure 11
DDR to SDR
data conversion
Select positive or
negative clock edge
for re-alignment
Compensate if DDR
data shifted by 1/2
clock cycle
data to
read FIFOs
MPMC_Clk_Mem
MPMC_Clk0
RDDATA_CLK_SEL
MPMC_Clk0
RDDATA_SWAP_RISE
SRL
Delay
Element
read enable from control path
read enable to data path
MPMC_Clk0
RDEN_DELAY
Figure 11: Static PHY Interface Read Logic
DS643_05_071307
The Static PHY processes the read data as follows:
1. First, the Static PHY registers the read data on a clock (MPMC_Clk_Mem), which is typically provided by an
additional Digital Clock Manager (DCM). This clock is, typically, a phase-shifted version of MPMC_Clk0. The
phase is set to maximize timing margin on the captured read data.
The read data goes through input flip-flops and is converted to Single Data Rate (SDR) data that is aligned on
the rising edge of MPMC_Clk_Mem.
2. The data is then re-registered into the main MPMC clock domain (MPMC_Clk0).
Depending on the phase relationship between MPMC_Clk_Mem and MPMC_Clk0, you might need to first
re-register the data on the negedge of MPMC_Clk0 before being registered on the positive edge. The selection
using positive or negative edges of MPMC_Clk0 depends on the relative phase of MPMC_Clk_Mem:
- If MPMC_Clk_Mem is 0 to +180 degrees ahead of MPMC_Clk0, register the data on the positive edge of
MPMC_Clk0.
- If MPMC_Clk_Mem is 0 to -180 degrees behind MPMC_Clk0, register the data on the negative edge of
MPMC_Clk0.
The C_STATIC_PHY_RDDATA_CLK_SEL parameter sets the default value for this selection. You can change this
value using the software interface at a later time, if necessary.
3. Next, data from the Static PHY passes through a selector to determine how the DDR data from memory is
aligned with respect to positive and negative edges of MPMC_Clk_Mem.
Depending upon board layout and clock frequency, it is possible that the data that is registered on the posedge
of MPMC_Clk_Mem should be registered on the negedge of MPMC_Clk_Mem.
DS643 February 22, 2013
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Product Specification